Zero power fuse sensing circuit for redundancy applications in memories

• US 6,618,311 B1
• Filed: 02/12/2002
• Issued: 09/09/2003
• Est. Priority Date: 02/12/2002
• Status: Active Grant

• Current Assignee: Arm Incorporated (SoftBank Group Corp.)
• Original Assignee: Artisan Components, Inc. (SoftBank Group Corp.)
• Inventors: Becker, Scott T.
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US10/074,559
• Time in Patent Office: 574 Days
• Field of Search: 365/200, 365/225.7, 365/204, 365/230.08, 365/189.11, 365/94, 365/96, 365/102, 327/525, 327/526, 327/524, 716/2
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/83 with reduced power consumption

Abstract

An invention is provided for a fuse state sensing circuit that senses the state of a fuse, which is coupled between a ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit further includes a keeper latch circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The keeper latch circuit is capable of latching the state of the fuse state sensing node. In addition, the keeper latch circuit stops supplying current to the fuse state sensing node when a predetermined rail voltage is reached if the fuse is intact. Also, when a predetermined rail voltage is reached and the fuse is blown, the keeper latch circuit continues to supply current to the fuse state sensing node.

Claims

1. A fuse state sensing circuit, comprising:

a fuse coupled between a ground rail and a fuse state sensing node, the fuse state sensing node indicating a state of the fuse when rail voltage is provided to the fuse state sensing circuit;

a capacitive element coupled to the fuse state sensing node, the capacitive element capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage, the capacitive element being configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element; and

a keeper latch circuit coupled to the fuse state sensing node in parallel with the capacitive element, the keeper latch circuit capable of latching the state of the fuse state sensing node, wherein the keeper latch circuit stops supplying current to the fuse state sensing node when a predetermined rail voltage is reached if the fuse is intact, and wherein the keeper latch circuit continues to supply current to the fuse state sensing node when a predetermined rail voltage is reached and the fuse is blown.

2. A fuse state sensing circuit as recited in claim 1, wherein the capacitive element is a capacitive configured transistor.

3. A fuse state sensing circuit as recited in claim 2, wherein the capacitive configured transistor is a p-channel transistor having a gate coupled to V_DD and a first terminal and a second terminal that are coupled together.

4. A fuse state sensing circuit as recited in claim 1, wherein the keeper latch circuit is comprised of an inverter having an input coupled to the fuse state sensing node and an output coupled to a transistor.

5. A fuse state sensing circuit as recited in claim 4, wherein the transistor is a p-channel transistor having a first terminal coupled to V_DD, a second terminal coupled to the fuse state sensing node, and a gate coupled to the output of the inverter.

6. A fuse state sensing circuit as recited in claim 5, wherein the inverter includes an n-channel transistor and a p-channel transistor, the n-channel transistor having a width greater than a width of the p-channel transistor.

7. A fuse state sensing circuit as recited in claim 1, wherein the fuse state sensing circuit is disposed within a fuse box, and wherein the fuse box is designed using a generator.

8. A fuse state sensing circuit, comprising:

a fuse coupled between a ground rail and a fuse state sensing node, the fuse state sensing node indicating a state of the fuse when rail voltage is provided to the fuse state sensing circuit;

a capacitive element coupled to the fuse state sensing node, the capacitive element capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage, the capacitive element being configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element; and

a pull up circuit coupled to the fuse state sensing node in parallel with the capacitive element, wherein the pull up circuit stops supplying current to the fuse state sensing node when a predetermined rail voltage is reached if the fuse is intact, and wherein the pull up circuit continues to supply current to the fuse state sensing node when the rail voltage is reached and the fuse is blown.

9. A fuse state sensing circuit as recited in claim 8, wherein the capacitive element is a capacitive configured transistor.

10. A fuse state sensing circuit as recited in claim 9, wherein the capacitive configured transistor is a p-channel transistor having a gate coupled to V_DD and a first terminal and a second terminal that are coupled together.

11. A fuse state sensing circuit as recited in claim 8, wherein the pull up circuit is comprised of a current enable transistor and a pull up transistor, the current enable transistor determining an amount of current provided by the pull up transistor.

12. A fuse state sensing circuit as recited in claim 11, wherein the current enable transistor is a p-channel transistor having a gate coupled to the fuse state sensing node, a first terminal coupled to V_DD, and a second terminal coupled to the gate of the pull up transistor.

13. A fuse state sensing circuit as recited in claim 12, wherein the pull up transistor is a p-channel transistor having a first terminal coupled to V_DD and a second terminal coupled to the fuse state sensing node.

14. A fuse state sensing circuit as recited in claim 13, wherein the pull up circuit further comprises a leakage transistor coupled to the gate of the pull up transistor.

15. A fuse state sensing circuit as recited in claim 8, wherein the fuse state sensing circuit is disposed within a fuse box, and wherein the fuse box is designed using a generator.

16. A method for sensing a fuse state for a redundancy application, comprising the operations of:

supplying an initial voltage to rail voltage;

providing an initial current to a fuse state sensing node utilizing a capacitive element, the capacitive element ceasing to provide current to the fuse state sensing node upon reaching a predetermined voltage threshold; and

supplying additional current to the fuse state sensing node when the fuse is blown utilizing a pull up circuit and a keeper latch circuit, wherein the pull up circuit and the keeper latch circuit stop supplying current to the fuse state sensing node when the fuse is intact.

17. A method as recited in claim 16, wherein the capacitive element is a p-channel capacitive configured transistor having a gate coupled to V_DD and a first terminal and a second terminal that are coupled together.

18. A method as recited in claim 16, wherein the pull up circuit is comprised of a current enable transistor and a pull up transistor, the current enable transistor determining an amount of current provided by the pull up transistor.

19. A method as recited in claim 16, wherein the keeper latch circuit is comprised of an inverter having an input coupled to the fuse state sensing node and an output coupled to a transistor, the transistor being a p-channel transistor having a first terminal coupled to V_DD, a second terminal coupled to the fuse state sensing node, and a gate coupled to the output of the inverter.

20. A method as recited in claim 19, wherein the inverter includes an n-channel transistor and a p-channel transistor, the n-channel transistor having a width greater than a width of the p-channel transistor.