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Method and architecture for reducing the power consumption for memory devices in refresh operations

  • US 6,618,314 B1
  • Filed: 03/04/2002
  • Issued: 09/09/2003
  • Est. Priority Date: 03/04/2002
  • Status: Expired due to Term
First Claim
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1. A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of:

  • enabling said background operations in one or more of said plurality of sections of said memory array when one or more control signals are in a first state and disabling said background operations in said one or more sections when said one or more control signals are in a second state; and

    presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said one or more sections.

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