Method and architecture for reducing the power consumption for memory devices in refresh operations

• US 6,618,314 B1
• Filed: 03/04/2002
• Issued: 09/09/2003
• Est. Priority Date: 03/04/2002
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Parent, Richard M., Fiscus, Timothy E., Chapman, David E.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/090,850
• Time in Patent Office: 554 Days
• Field of Search: 365/222, 365/227, 365/230.03
• US Class Current: 365/227
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.

Claims

1. A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of:

enabling said background operations in one or more of said plurality of sections of said memory array when one or more control signals are in a first state and disabling said background operations in said one or more sections when said one or more control signals are in a second state; and

presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said one or more sections.

2. The method according to claim 1, wherein said background operations comprise a refresh operation.

3. The method according to claim 1, wherein said plurality of sections comprise quadrants.

4. The method according to claim 1, wherein said background operations comprise parity checking.

5. The method according to claim 1, further comprising:

controlling, in response to said one or more first control signals, an operation of said one or more periphery array circuits, wherein said periphery array circuits each comprise one or more circuits from the group consisting of sense amplifiers, column multiplexer circuits, equalization circuits, and wordline driver circuits.

6. The method according to claim 1, further comprising:

generating one of said one or more control signals for each of said plurality of sections of said memory array.

7. The method according to claim 1, wherein said one or more control signals are generated in response to an address signal.

8. The method according to claim 1, further comprising:

generating said one or more first control signals in response to a refresh enable signal.

9. The method according to claim 8, further comprising generating a memory cell selection signal comprising a binary numerical representation configured such that a single bit changes between successive numbers in response to said refresh enable signal.

24. The method according to claim 1, wherein said one or more decoded address signals comprise one or more decoded row address signals and one or more decoded column address signals.

10. An apparatus comprising:

means for enabling a background operation in one or more sections of a memory array when one or more control signals have a first state and disabling said background operation in said one or more sections when said one or more control signals have a second state; and

means for presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said one or more sections.

11. An apparatus comprising:

a memory array comprising a plurality of sections, wherein each of said sections comprises (i) a plurality of memory cells and (ii) periphery array circuitry configured to control access to said plurality of memory cells; and

a control circuit configured to present one or more control signals and one or more decoded address signals to said periphery array circuitry of said plurality of sections, wherein a background operation in one or more of said plurality of sections of said memory array is (i) enabled when said one or more control signals are in a first state and (ii) disabled when said one or more control signals are in a second state.

12. The apparatus according to claim 11, wherein said background operation comprises a refresh operation.

13. The apparatus according to claim 11, wherein each of said one or more control signals is configured to control one or more array control signals of a corresponding section.

14. The apparatus according to claim 11, wherein said periphery array circuitry comprises one or more sense amplifiers configured to sense a memory cell state in response to said one or more control signals and said one or more decoded address signals.

15. The apparatus according to claim 11, wherein said periphery array circuitry is configured to generate one or more wordline signals in response to said one or more control signals and said one or more decoded address signals.

16. The apparatus according to claim 11, wherein said periphery array circuitry comprises equalization circuitry configured to equalize one or more bitlines to a predetermined voltage potential in response to said one or more control signals and said one or more decoded address signals.

17. The apparatus according to claim 11, wherein said periphery array circuitry comprises column multiplexing circuitry.

18. The apparatus according to claim 11, wherein said one or more control signals are generated in response to an address signal.

19. The apparatus according to claim 11, wherein each of said memory cells comprises a dynamic storage element.

20. The apparatus according to claim 11, wherein said background operation comprises parity checking.

21. The apparatus according to claim 11, wherein said one or more decoded address signals comprise one or more decoded row address signals and one or more decoded column address signals.

22. The apparatus according to claim 11, wherein said periphery array circuitry of each of said plurality of sections is configured to control said plurality of memory cells of each of said plurality of sections in response to (i) said one or more control signals and (ii) said one or more decoded address signals.

23. The apparatus according to claim 11, wherein said memory array comprises a plurality of blocks and each block of said plurality of blocks comprises two or more of said plurality of sections.