System and method for controlling power states of a memory device via detection of a chip select signal
First Claim
1. A memory system, comprising:
- at least one memory device for storing data;
a memory controller that sends data and signals to the at least one memory device;
a chip select line that connects the memory controller and the at least one memory device, or a portion thereof, the chip select line allowing the transmission of a chip select signal to the at least one memory device, or the portion thereof, the chip select signal selecting the at least one memory device, or the portion thereof, to sample commands; and
an edge detection device implementing logic for detecting an edge of an assertion of the chip select signal, wherein when the logic detects the edge of the chip select signal provided to the at least one memory device, or the portion thereof, that is in a power state lower than its active state, the at least one memory device, or the portion thereof, is automatically moved from the lower power state to a higher power state, and all clock inputs to the at least one memory device, or the portion thereof, are disabled to conserve power when the at least one memory device, or the portion thereof, is in the lower power state.
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Accused Products
Abstract
A memory system and a method for controlling power states of a memory device, or a portion thereof, are provided. The memory system includes memory devices, such as DRAMs, a memory controller, chip select lines, and logic for detecting chip select signals from the chip select lines. Each memory device, or a portion therein, is connected to the memory controller by a chip select line. Each chip select line allows the transmission of a chip select signal to a corresponding memory device, or a corresponding portion of the memory device, to select the corresponding memory device, or a portion thereof, to receive commands. Logic is provided to detect the chip select signal. When the logic detects a chip select signal provided to a corresponding memory device, or a portion thereof, that is in a power state lower than its idle state, the memory device, or a portion thereof, is automatically moved from the lower power state to a higher power state.
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Citations
14 Claims
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1. A memory system, comprising:
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at least one memory device for storing data;
a memory controller that sends data and signals to the at least one memory device;
a chip select line that connects the memory controller and the at least one memory device, or a portion thereof, the chip select line allowing the transmission of a chip select signal to the at least one memory device, or the portion thereof, the chip select signal selecting the at least one memory device, or the portion thereof, to sample commands; and
an edge detection device implementing logic for detecting an edge of an assertion of the chip select signal, wherein when the logic detects the edge of the chip select signal provided to the at least one memory device, or the portion thereof, that is in a power state lower than its active state, the at least one memory device, or the portion thereof, is automatically moved from the lower power state to a higher power state, and all clock inputs to the at least one memory device, or the portion thereof, are disabled to conserve power when the at least one memory device, or the portion thereof, is in the lower power state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory device, comprising:
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a chip select pin for receiving a chip select signal that selects the memory device, or a portion thereof, to receive a command to be operated on the memory device;
command pins for receiving the command; and
an edge detection device implementing logic for detecting an edge of an assertion of the chip select signal, wherein when the chip select signal is received by the memory device, or the portion thereof, that is in a power state lower than its active state, the logic detects the edge of the chip select signal and the command received by the memory device, the memory device, or the portion thereof, being automatically moved from the lower power state to a higher power state, and all clock inputs to the at least one memory device, or the portion thereof, are disabled to conserve power when the at least one memory device, or the portion thereof, is in the lower power state. - View Dependent Claims (12, 13, 14)
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Specification