Prototype development system and method

• US 6,618,842 B2
• Filed: 10/26/2001
• Issued: 09/09/2003
• Est. Priority Date: 07/14/1998
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Hasslen, Robert J. III, Nicolino, Sam J. Jr., Vogel, Ernest P., Martinez, Fernando G.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Whitmore, Stacy
• Application Number:
  US10/045,248
• Publication Number:
  US 20020131244A1
• Time in Patent Office: 683 Days
• Field of Search: 324/754, 324/755, 324/763, 324/756, 324/757, 324/500, 716/1, 716/4, 716/15
• US Class Current: 716/137
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H05K 1/029 having a programmable lay-out, i.e. adapted for choosing between a few possibilities
• CPC Class Codes: H05K 1/14 Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 1/148 Arrangements of two or more hingeably connected rigid printed circuit boards, i.e. connected by flexible means
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49208 by assembling plural parts

Abstract

A prototype development apparatus includes a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of the IC sites, and a plurality of logic board connector sites (LBCSs) configured to provide access to a number of the logic traces and each adapted to receive a connector. Additionally, a mezzanine board (MB) has a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and configured to provide access to a number of mezzanine traces interconnecting the LBCSs. The MB board is coupled to the LB and a portion of the logic traces are coupled to a portion of the mezzanine traces. In another embodiment the MB does not have any active components. This is because in this embodiment, the MB is configured to connect the pins of the connector sites according to a predetermined program. A method of prototyping a target circuit generates a netlist representative of the target circuit, divides the netlist into portions to be programmed into ICs on the LB and portions to be fabricated on the MB, such that the target circuit is configured from both the LB and the MB. Advantages of the present invention include providing a cost-effective technique for developing a prototype that combines the advantages of the custom prototype speed with the flexibility of the re-programmable emulators.

Claims

1. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces;

said LB including a logic board clock connector site (LBCCS) coupled to a number of clock traces and adapted to receive a clock connector;

a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs; and

a clock mezzanine board (CMB) having a clock mezzanine board connector site (CMBCS) adapted to receive said clock connector and coupled to a number of mezzanine clock traces.

2. The prototype development apparatus of claim 1, wherein:

said ICs are programmable grid arrays (PGAs).

3. The prototype development apparatus of claim 1, wherein:

said MB does not include an active component.

4. The prototype development apparatus of claim 1, wherein:

said LBCSs each include a plurality of pads each coupled to a logic trace;

said LBCSs each include a pair of holes in said LB adjacent to said pads;

said MBCSs each include a plurality of pads each coupled to a mezzanine trace; and

said MBCSs each include a pair of holes in said LB adjacent to said pads; and

wherein each of said connectors includes;

a flexible printed circuit board having a plurality of traces with raised dots on a first side adapted to connect to a plurality of pads and raised dots on a second side adapted to connect to a plurality of pads;

a first pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said LB, and configured such that when said threaded bolts are tightened, to press said dots on said first side to said plurality of pads in said LBCS; and

a second pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said MB, and configured such that when said threaded bolts are tightened, to press dots on said second side to said plurality of pads in said MBCS.

5. The prototype development apparatus of claim 1, wherein:

said LBCSs each include a plurality of pads disposed in a substantially rectangular pattern each coupled to a logic trace;

said LBCSs each include a pair of holes in said LB adjacent to opposite sides of said rectangular pattern;

said MBCSs each include a plurality of pads disposed in a substantially rectangular pattern each coupled to a mezzanine trace; and

said MBCSs each include a pair of holes in said LB adjacent to opposite sides of said rectangular pattern; and

wherein each of said connectors includes;

a flexible printed circuit board having a plurality of traces with raised dots on a first side adapted to connect to a plurality of pads and raised dots on a second side adapted to connect to a plurality of pads;

a first pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said LB, and configured such that when said threaded bolts are tightened, to press said dots on said first side to said plurality of pads in said LBCS; and

a second pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said MB, and configured such that when said threaded bolts are tightened, to press dots on said second side to said plurality of pads in said MBCS.

6. The prototype development apparatus of claim 1, wherein:

said LBCSs each include a plurality of raised dots each coupled to a logic trace;

said LBCSs each include a pair of holes in said LB adjacent to said raised dots;

said MBCSs each include a plurality of raised dots each coupled to a mezzanine trace;

said MBCSs each include a pair of holes in said LB adjacent to said raised dots; and

wherein each of said connectors includes;

a flexible printed circuit board having a plurality of connector traces exposed on a first side and adapted to connect to a plurality of dotted pads, and exposed on a second side and adapted to connect to a plurality of dotted pads;

a first pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said LB, and configured such that when said threaded bolts are tightened, to press said connector traces exposed on said first side to said plurality of dotted pads in said LBCS; and

a second pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said MB, and configured such that when said threaded bolts are tightened, to press said connector traces exposed on said second side to said plurality of dotted pads in said MBCS.

7. The prototype development apparatus of claim 1, wherein:

said LBCSs each include a plurality of raised dots disposed in a substantially rectangular pattern each coupled to a logic trace;

said LBCSs each include a pair of holes in said LB adjacent to opposite sides of said rectangular pattern;

said MBCSs each include a plurality of raised dots disposed in a substantially rectangular pattern each coupled to a mezzanine trace;

said MBCSs each include a pair of holes in said LB adjacent to opposite sides of said rectangular pattern; and

wherein each of said connectors includes;

a flexible printed circuit board having a plurality of connector traces exposed on a first side and adapted to connect to a plurality of dotted pads, and exposed on a second side and adapted to connect to a plurality of dotted pads;

a first pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said LB, and configured such that when said threaded bolts are tightened, to press said connector traces exposed on said first side to said plurality of dotted pads in said LBCS; and

a second pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said MB, and configured such that when said threaded bolts are tightened, to press said connector traces exposed on said second side to said plurality of dotted pads in said MBCS.

8. The prototype development apparatus of claim 4, wherein:

each of said connectors further includes a resilient backing disposed behind said flexible printed circuit board to press said dots on said first side to said plurality of pads in said LBCS and to press said dots on said second side to said plurality of dotted pads in said MBCS.

9. The prototype development apparatus of claim 6, wherein:

each of said connectors further includes a resilient backing disposed behind said flexible printed circuit board to press said connector traces exposed on said first side to said plurality of dotted pads in said LBCS and to press said connector traces exposed on said second side to said plurality of dotted pads in said MBCS.

10. The prototype development apparatus of claim 4, wherein:

each of said connectors has a connect density greater than about 100 dots/inch².

11. The prototype development apparatus of claim 6, wherein:

each of said connectors has a connect density greater than about 100 dots/inch².

12. The prototype development apparatus of claim 1, wherein:

said LB includes a programmable delay buffer coupled to said clock traces and configured to selectively delay signals on said clock traces.

13. The prototype development apparatus of claim 1, wherein:

said LB includes a logic board incremental connector site LBICS coupled to a number of said logic traces and adapted to receive an incremental connector, and

said prototype development apparatus further comprises an incremental mezzanine board (1MB) having an incremental mezzanine board connector site (IMBCS) adapted to receive said incremental connector and coupled to a number of incremental mezzanine traces.

14. The prototype development apparatus of claim 1, further comprising:

an adapter board (AB) having an IC connector adapted to couple to a LB IC site and configured to communicate signals with said signal traces.

16. The prototype development apparatus of claim 1, further comprising:

a buffer board coupled to said MB and having a plurality of buffer board connector sites (BBCSs) coupled to a number of buffer traces and adapted to receive a connector; and

wherein said BBCSs are configured to couple with an external circuit.

17. The prototype development apparatus of claim 1, further comprising:

an auxiliary logic board (ALB) coupled to said MB and including a plurality of components.

18. The prototype development apparatus of claim 1, further comprising:

a second mezzanine board (2MB) including a plurality of second mezzanine board connector sites (2MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs.

19. The prototype development apparatus of claim 1, wherein:

a plurality of said mezzanine traces are spare traces.

20. The prototype development apparatus of claim 1, wherein:

at least one of said LBCSs includes a companion logic board connector site (CLBCS) coupled to the same traces as said LBCS.

21. The prototype development apparatus of claim 1, wherein:

at least one of said MBCSs includes a companion mezzanine board connector site (CMBCS) coupled to the same traces as said MBCS.

22. The prototype development apparatus of claim 1, wherein:

a first portion of said logic traces are coupled between at least two IC sites and a second portion of said logic traces are coupled between at least one IC site and a LBCS.

23. The prototype development apparatus of claim 1, wherein:

said MB includes an active component.

24. The prototype development apparatus of claim 1, wherein:

said MB includes a state hold circuit coupled to at least one of said mezzanine traces and configured to hold a signal at one of a plurality of logic levels until driven to a different level.

25. The prototype development apparatus of claim 1 wherein:

said MB includes a computer connector configured to couple said MB to an external computer structure.

26. The prototype development apparatus of claim 2, wherein:

said LB includes a logic board clock connector site LBCCS coupled to a number of said clock traces and adapted to receive a clock connector,

said prototype development apparatus further comprises a clock mezzanine board (CMB) having a clock mezzanine board connector site (CMBCS) adapted to receive said clock connector and coupled to a number of mezzanine clock traces;

said prototype development apparatus further comprises a buffer board disposed between said LB and said MB and having a plurality of buffer board connector sites (BBCSs) coupled to a number of buffer traces and adapted to receive a connector, and

one of said BBCSs is coupled to said LB and another of said BBCSs is coupled to said MB.

15. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces;

mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

said MB including a mezzanine board probe connector site MBPCS coupled to a number of said mezzanine traces and adapted to receive a probe connector.

27. A method of constricting a prototype apparatus comprising:

fabricating a plurality of logic boards (LBs) each including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) coupled to a number of said logic traces and each adapted to receive a connector;

fabricating a plurality of different mezzanine boards (MBs) having a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of differently routed mezzanine traces interconnecting said MBCSs; and

coupling each of said LBs and said MBs via a plurality of connectors connected to said LBCSs and said MBCSs.

28. A method of prototyping a target circuit using a logic board (LB) having a plurality of programmable integrated circuits (PICs) and a number of logic traces, and a mezzanine board (MB), comprising the steps of:

generating a netlist representative of said target circuit;

dividing said netlist into first portions to be programmed into said PICs and second portions to interconnect said PICs;

programming said first portions into said PICs;

fabricating said MB including mezzanine traces based on said second portions; and

coupling said logic traces and said mezzanine traces such that said target circuit is configured from both said LB and said MB.

29. The method of claim 28, further comprising the step of:

communicating signals among said PICs exclusively via said MB.

30. The method of claim 28, wherein a first portion of said logic traces are coupled between at least two IC sites and a second portion of said logic traces are coupled between at least one IC site and a logic board connector site, and said method further comprises the steps of:

communicating a first set of signals among said PICs via said LB; and

communicating a second set of signals among said PICs via said MB.