Semiconductor device and method of manufacturing the same

• US 6,620,653 B2
• Filed: 09/25/2001
• Issued: 09/16/2003
• Est. Priority Date: 09/28/2000
• Status: Expired due to Term

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsudai, Tomoko, Hattori, Hidetaka, Nakagawa, Akio
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/961,361
• Publication Number:
  US 20020048855A1
• Time in Patent Office: 721 Days
• Field of Search: 438/135, 438/137, 438/138, 438/542, 438/546, 257/133, 257/137, 257/146, 257/350, 257/370, 257/378
• US Class Current: 438/135
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

Claims

1. A semiconductor device comprising:

a first conductive type first base layer comprising a semiconductor substrate;

a second conductive type collector layer whose thickness is set to 1 μ

m or less and located on a side of a first surface of said first base layer;

a first conductive type buffer layer between said first base layer and said collector layer;

a second conductive type second base layer on a side of a second surface of said first base layer;

a first conductive type emitter layer in said second base layer; and

a gate electrode above said second base layer between said emitter layer and said first base layer.

2. The semiconductor device according to claim 1:

wherein each of said collector layer, said second base layer and said emitter layer comprises a diffusion layer in said semiconductor substrate, a thickness of said collector layer is defined by a depth of said collector layer from said first surface of said first base layer.

3. The semiconductor device according to claim 1:

further comprising a second conductive type impurity layer disposed in said second base layer between said emitter layer and said first base layer, said second conductive type impurity layer is different from said second base layer.

4. The semiconductor device according to claim 1:

wherein said second base layer between said emitter layer and said first base layer becomes a channel region of a field-effect transistor.

5. The semiconductor device according to claim 1:

wherein said second base layer has a groove, and said emitter layer is disposed along an edge of said groove.

6. The semiconductor device according to claim 1:

further comprising a first conductive type low resistant layer in said first base layer adjacent to said second base layer and having a resistant value lower than that of said first base layer.

7. The semiconductor device according to claim 1:

wherein in a condition that a thickness of said first base layer is defined as L, a cell comprises said first base layer, said collector layer, said buffer layer, said second base layer, said emitter layer and said gate electrode, and a half size of said cell is defined W, the following relation is satisfied;

8. The semiconductor device according to claim 1:

wherein a thickness of said semiconductor substrate is 70 μ

m or less.

9. The semiconductor device according to claim 1:

wherein said semiconductor device is an IGBT.

14. The semiconductor device according to claim 1:

wherein said semiconductor device is an IGBT.

10. A semiconductor device comprising:

a first conductive type first base layer;

a second conductive type collector layer on a side of a first surface of said first base layer;

a first conductive type buffer layer between said first base layer and said collector layer;

a second conductive type second base layer on a side of a second surface of said first base layer;

a first conductive type emitter layer in said second base layer; and

a gate electrode above said second base layer between said emitter layer and said first base layer;

wherein the following condition is satisfied;

11. The semiconductor device according to claim 10:

wherein said first base layer comprises a semiconductor substrate, each of said collector layer, said second base layer and said emitter layer comprises a diffusion layer in said semiconductor substrate, a thickness of said collector layer is set to 1 μ

m or less.

12. The semiconductor device according to claim 10:

wherein a thickness of said semiconductor substrate is 70 μ

m or less.

13. The semiconductor device according to claim 10:

wherein a peak value of an impurity density in said buffer layer is set to 5×

10¹⁶ atoms/cm³ or higher.

15. A manufacturing method of a semiconductor device comprising:

implanting impurities into a power device area and a control element area by ion-implantation using one mask, and forming a first impurity layer in said power device area and a second impurity layer in said control element area;

forming a power device including said first impurity layer; and

forming a control element including said second impurity layer.

16. The manufacturing method according to claim 15:

wherein said impurity is negative impurity, said first impurity layer is an emitter layer of an IGBT, and said second impurity layer is a source/drain region of a negative channel field-effect transistor.

17. The manufacturing method according to claim 16:

wherein said IGBT is of horizontal type.

18. The manufacturing method according to claim 15:

wherein said impurity is positive impurity, said first impurity layer is a collector layer of an IGBT, said second impurity layer is a source/drain region of a positive channel field-effect transistor.

19. The manufacturing method according to claim 18:

wherein said IGBT is of horizontal type.

20. The manufacturing method according to claim 15:

wherein said impurity is negative impurity, said first impurity layer is an emitter layer of the IGBT, said second impurity layer is a collector region and an emitter region of an NPN type bipolar transistor.

21. The manufacturing method according to claim 20:

wherein said IGBT is of horizontal type.

22. The manufacturing method according to claim 15:

wherein said impurity is positive impurity, said first impurity layer is a collector layer of an IGBT, and said second impurity layer is an emitter region and a collector region of a PNP type bipolar transistor.

23. The manufacturing method according to claim 22:

wherein said IGBT is of horizontal type.

24. A manufacturing method of a semiconductor device comprising:

forming a conductive film on each of a power device area and a control element area, etching said conductive film by RIE, forming a first electrode in said power device area, forming a second electrode in said control element area;

forming a power device including said first electrode; and

forming a control element including said second electrode.

25. The manufacturing method according to claim 24:

wherein said first electrode is a gate electrode of an IGBT, said second electrode is a gate electrode of a field-effect transistor.