Manufacture of trench-gate semiconductor devices

• US 6,620,669 B2
• Filed: 05/21/2002
• Issued: 09/16/2003
• Est. Priority Date: 05/29/2001
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: inʼt Zandt, Michael A. A., Hijzen, Erwin A.
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US10/152,208
• Publication Number:
  US 20020179950A1
• Time in Patent Office: 483 Days
• Field of Search: 257/301, 438/242, 438/209, 438/156, 438/259, 438/270, 438/206
• US Class Current: 438/206
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical power transistor trench-gate semiconductor device has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25) (FIG. 6). While an n-type layer (14) suitable for drain regions still extends to the semiconductor body surface (10a), gate material (11) is deposited in silicon dioxide insulated (17) trenches (20) and planarised to the top of the trenches (20) in the active (100) and inactive (200) areas. Implantation steps then provide p-type channel-accommodating body regions (15A) in the active area (100) and p-type regions (15B) in the inactive area (200), and then source regions (13) in the active area (100). Further gate material (111) is then provided extending from the gate material (11) in the inactive area (200) and onto a top surface insulating layer (17B) for contact with the gate electrode (25). The channel profiles of the device are optimised by providing the p-type regions (15A) after the trench insulation (17), and voltage breakdown at the bottom corners of the trenches (20) is suppressed by providing the p-type regions (15B) in the inactive area (200).

Claims

1. A method of manufacturing a vertical power transistor trench-gate semiconductor device, the device comprising:

a semiconductor body with trenches extending into the semiconductor body from a surface thereof and an insulating layer provided between gate material in the trenches and the semiconductor body adjacent the trenches;

wherein the device has an active transistor cell area, each transistor cell having source and drain regions which are separated by a channel-accommodating body region adjacent a trench-gate, and a source electrode contacting the source regions on the semiconductor body surface and being insulated from the gate material in the trenches; and

wherein the device has an inactive area without source regions, said insulating layer extending from the trenches to provide a top surface insulating layer on the semiconductor body surface in the inactive area, further gate material extending from the gate material in the trenches in the inactive area and onto the top surface insulating layer, and a gate electrode contacting the further gate material;

the method including the steps of;

(a) providing the semiconductor body with a first layer extending to the semiconductor body surface in the active and inactive areas, the first layer being of a first conductivity type suitable for the drain regions;

(b) forming the trenches extending into the first layer in the active and inactive areas;

(c) while the first layer still extends to the semiconductor body surface, providing the insulating layer in the trenches in the active and inactive areas, and providing the top surface insulating layer in the inactive area;

(d) depositing a first material in the trenches and planarising the first material to the top of the trenches in the active and inactive areas;

(e) after steps (c) and (d), forming a second layer extending from the semiconductor body surface in the active and inactive areas, the second layer being of a second conductivity type, opposite to the first conductivity type, suitable for the channel-accommodating body regions in the active area;

(f) after step (e), forming the source regions in the active area; and

(g) also after step (e), providing the further gate material in the inactive area.

2. A method as claimed in claim 1, wherein in step (c) the insulating layer in the trenches and the top surface insulating layer in the inactive area are formed by oxidation of the semiconductor body first layer.

3. A method as claimed in claim 1, wherein the first material which is deposited and planarised in step (d) is the device gate material.

4. A method as claimed in claim 3, wherein the first material is polycrystalline silicon.

5. A method as claimed in claim 3, wherein the gate material and the further gate material have the same composition.

6. A method as claimed in claim 1, wherein after step (e) and before step (g) the first material is removed from the trenches, and wherein in step (g) a second material is deposited in the trenches and on the top surface insulating layer in the inactive area, and the second material is patterned to provide the device gate material and the device further gate material.

7. A method as claimed in claim 6, wherein the second material is polycrystalline silicon.

8. A method as claimed in claim 6, wherein the second material is metal.

9. A method as claimed in claim 1, wherein in step (c) the insulating layer in the trenches, the top surface insulating layer in the inactive area and a further top surface insulating layer in the active area are formed simultaneously, and wherein the second layer is formed in step (e) using dopant implantation through the top surface insulating layer and through the further top surface insulating layer.

10. A method as claimed in claim 9, wherein the source regions are formed in step (f) an using dopant implantation through the further top surface insulating layer, and wherein the further top surface insulating layer is removed before providing the source electrode.

11. A method as claimed in claim 1, wherein in step (f) an applied mask is used to define areas for the source regions.

12. A method as claimed in claim 1, wherein the source electrode is insulated from the gate material in the trenches by prior application and patterning of insulating material to provide gate insulating overlayers in the active area.

13. A method as claimed in claim 1, wherein the trenches are formed as a connected trench network having the same pattern in the active and inactive areas, the transistor cells in the active area each being surrounded by the trench network and contacted by the provided source electrode at the semiconductor body surface, and isolated cells of the second layer in the inactive area each being surrounded by the trench network and not contacted by the provided source electrode.

14. A method as claimed in claim 1, wherein the trenches in the inactive area are formed as a pattern of stripe-shaped trenches extending from the active area to the inactive area, wherein stripe-shaped regions of the second layer are formed to extend between the stripe-shaped trenches from the active area to the inactive area, and wherein the source electrode is provided to contact the stripe-shaped regions of the second layer at the semiconductor body surface.