Semiconductor trench device with enhanced gate oxide integrity structure

• US 6,620,691 B2
• Filed: 11/20/2001
• Issued: 09/16/2003
• Est. Priority Date: 06/16/2000
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): Owens, Beth E.
• Application Number:
  US10/042,558
• Publication Number:
  US 20020061623A1
• Time in Patent Office: 665 Days
• Field of Search: 438/268, 438/270, 438/272
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.

Claims

1. A method for making a trench DMOS, comprising the steps of:

providing an semiconductor device comprising a first region having a first conductivity type and a second region having a second conductivity type, the article having first and second trenches which are in communication with the first and second regions;

depositing a first electrically insulating layer over the surface of the first trench, the first insulating layer having a mean thickness over the first trench of t₁; and

depositing a second electrically insulating layer over the surface of the second trench, said second insulating layer having a mean thickness over the second trench of t₂;

wherein the ratio t₁/t₂ is at least about 1.2

2. The method of claim 1, wherein t₁/t₂ is at least about 1.5.

3. The method of claim 1, wherein t₁/t₂ is at least about 2.

4. The method of claim 1, wherein t₁ is within the range of about 600 to about 840 angstroms.

5. The method of claim 1, wherein t₁ is within the range of about 750 to about 1050 angstroms.

6. The method of claim 1, wherein t₁ is within the range of about 1000 to about 1400 angstroms.

7. The method of claim 1, wherein the first and second insulating layers are oxide layers.

8. The method of claim 7, wherein the first and second insulating layers comprise silicon oxide.

9. The method of claim 1, further comprising the step of depositing polycrystalline silicon into the first and second trenches.

10. The method of claim 1, wherein the first insulating layer has an essentially uniform thickness over the first trench.

11. The method of claim 1, wherein the first region comprises an n doped epitaxial layer, and wherein the second region is a p type diffusion layer.

12. The method of claim 11, wherein the semiconductor device further comprises an n+ doped epitaxial layer, wherein the p type diffusion layer is disposed on a first side of the n doped epitaxial layer, and wherein the n+ doped layer is disposed on a second side of the n doped epitaxial layer.

13. A trench DMOS device made in accordance with claim 1, said trench DMOS device comprising an active portion and a termination portion, and wherein the first trench is disposed in the termination portion and the second trench is disposed in the active portion.

14. A power MOSFET made in accordance with the method of claim 13.