Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication

• US 6,620,713 B2
• Filed: 01/02/2002
• Issued: 09/16/2003
• Est. Priority Date: 01/02/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Arghavani, Reza, Chau, Robert, Doczy, Mark, Roberds, Brian
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/038,410
• Publication Number:
  US 20030124871A1
• Time in Patent Office: 622 Days
• Field of Search: 438/200, 438/287, 438/488, 438/585, 438/197
• US Class Current: 438/585
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.

Claims

1. A method of forming a semiconductor device comprising:

depositing a high-k gate dielectric layer on a substrate;

depositing a gate electrode on said gate dielectric layer by evaporating silicon crystals to form said gate electrode, said gate electrode including a hydrogen-free silicon layer;

treating said gate electrode such that said gate electrode is conductive; and

converting said silicon crystals into silicon vapors in a low vacuum chamber having a pressure less than or equal to 1 mTorr and a temperature at a boiling point of said silicon crystals; and

flowing said silicon vapors into a deposition chamber, said deposition chamber houses said substrate; and

condensing said silicon vapors on said gate dielectric to form said gate electrode, said deposition chamber being remote from said low vacuum chamber.

2. A method as in claim 1 further comprising:

depositing a polysilicon layer on said hydrogen-free silicon layer such that said hydrogen-free silicon layer is located between said high-k gate dielectric layer and said polysilicon layer, and

treating said polysilicon layer such that said polysilicon layer is conductive.

3. A method as in claim 2 wherein said polysilicon layer includes hydrogen impurities.

4. A method as in claim 1 further comprising:

depositing a silicon layer on said hydrogen-free silicon layer such that said hydrogen-free silicon layer is located between said high-k gate dielectric layer and said silicon layer; and

treating said silicon layer such that said silicon layer is conductive.

5. A method as in claim 4 wherein said silicon layer includes hydrogen impurities.

6. A method as in claim 1 wherein said depositing of said gate electrode on said gate dielectric is such that said gate electrode has a thickness in a range of approximately 25-1000 angstroms and wherein said depositing of said gate dielectric layer on said substrate is such that said gate dielectric layer has a thickness in a range of approximately 10-200 angstroms.