Low resistivity deep trench fill for DRAM and EDRAM applications

• US 6,620,724 B1
• Filed: 05/09/2002
• Issued: 09/16/2003
• Est. Priority Date: 05/09/2002
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG, International Business Machines Corporation
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation
• Inventors: Rousseau, Jean-Marc, Hauf, Manfred, Schumann, Dirk, Shepard, Joseph F. Jr., Goldbach, Matthias, Sell, Bernhard, Jammy, Rajarao, Tews, Helmut Horst, Schroeder, Uwe, Seidl, Harald, McStay, Irene
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US10/142,518
• Time in Patent Office: 495 Days
• Field of Search: 438/628, 438/629, 438/643, 438/644, 438/648, 438/653, 438/654, 438/677, 438/687, 438/633, 438/637, 438/695, 438/763, 438/707, 257/751, 257/762, 257/750, 257/758, 257/622
• US Class Current: 438/628
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

Claims

1. A method of fabricating a semiconductor device comprising:

(a) forming a trench in a semiconductor substrate, the trench including sidewalls defining a trench depth and a top opening defining a trench width, the sidewalls being substantially covered with a dielectric material; and

(b) depositing fill material having a resistivity below 5000 μ

Ω

·

cm on the dielectric material within the trench by flowing a first gas and a second gas together over the trench at a selected temperature and pressure, the first gas including a base material and the second gas including a dopant, wherein flowing the first and second gases together facilitates in situ doping of the base material.

2. The method of claim 1, wherein the trench depth relative to the trench width defines an aspect ratio of at least 20:

1.

3. The method of claim 1, wherein the selected temperature is between 400°

C. and 700°

C.

4. The method of claim 3, wherein the selected temperature is between 500°

C. and 600°

C.

5. The method of claim 4, wherein the selected pressure is between 100 Torr and 1000 Torr.

6. The method of claim 1. further comprising applying a relatively low temperature proximate to a top surface of the semiconductor substrate and a relatively high temperature proximate to a bottom surface of the semiconductor substrate, whereby the temperature difference between the relatively low and high temperatures acts to reduce bread loafing and improve conformality.

7. The method of claim 1, wherein the dopant is selected from the group consisting of As, Sb and P.

8. The method of claim 1, wherein the base material is selected from the group consisting of Si and SiGe.

9. The method of claim 8, wherein the base material is Si and the first gas containing Si is selected from the group consisting of SiH₄, Si₂H₆, TCS, DCS and HDS.

10. The method of claim 9, wherein the dopant is As, the second gas is AsH₃ and flowing the first and second gases forms the fill material of Si with As having a dopant concentration of between 1×

10¹⁷ and 5×

10²¹ atoms/cm³.

11. The method of claim 8, wherein the base material is SiGe, the dopant is As and the second gas is AsH₃, and flowing the first and second gases forms the fill material of SiGe doped with As having a dopant concentration of between 1×

10¹⁷ and 1×

10²² atoms/cm³.

12. The method of claim 11, wherein the first gas includes GeH₄.

13. A method of fabricating a semiconductor device comprising:

(a) forming a trench in a semiconductor substrate, the trench including sidewalls defining a trench depth and a top opening defining a trench width, the sidewalls being substantially covered by a dielectric material;

(b) forming a layer of fill material having a resistivity below about 5000 μ

Ω

·

cm on the dielectric material at a first temperature and a first pressure, the fill material being formed by depositing a base layer having a thickness less than 50 nm on the dielectric material; and

(c) soaking the base layer with a gas containing a dopant at a second temperature and a second pressure until the base layer is coated with the dopant.

14. The method of claim 13, wherein the trench depth relative to the trench width defines an aspect ratio of at least 20:

1.

15. The method of claim 13, wherein the dopant is selected from the group consisting of As, Sb and P.

16. The method of claim 13, wherein the base layer is selected from the group consisting of amorphous Si and SiGe.

17. The method of claim 16, wherein the base layer is SiGe and the method includes forming a first layer of amorphous Si on the dielectric material before the SiGe is formed.

18. The method of claim 13, further including repeating forming the base layer and soaking the base layer between one and five times.

19. The method of claim 13, further comprising forming a capping layer over the fill material, whereby the capping layer minimizes outdiffusion of the dopant.

20. The method of claim 19, wherein the capping layer is Si.

21. The method of claim 13, further including annealing the semiconductor substrate such that the dopant migrates into the base layer.

22. The method of claim 13, wherein the second temperature is between 500°

C. and 650°

C. and the second pressure is between 50 mTorr and 760 mTorr.

23. A method of fabricating a semiconductor device comprising:

(a) forming a trench in a semiconductor substrate, the trench including sidewalls defining a trench depth and a top opening defining a trench width, the sidewalls being substantially covered by a dielectric material;

(b) forming a layer of fill material having a resistivity of below about 5000 μ

Ω

·

cm on the dielectric material at a first temperature and a first pressure, the fill material being formed by depositing a base layer having a thickness less than 50 nm; and

(c) diffusing a dopant into the base layer at a second temperature and a second pressure.

24. The method of claim 23, wherein the dopant is selected from the group consisting of As, Sb and P.

25. The method of claim 23, wherein the base layer is selected from the group consisting of Si and SiGe.

26. The method of claim 25, wherein the base layer is SiGe and the method includes forming a first layer of amorphous Si on the dielectric material before the SiGe is formed.

27. The method of claim 23, wherein the second temperature is between 850°

C. and 1100°

C. and the second pressure is between 1 Torr and 100 Torr.

28. The method of claim 23, wherein the first temperature is between 500°

C. and 650°

C. and the first pressure is between 50 mTorr and 760 mTorr.

29. The method of claim 28, wherein the first temperature is between 525°

C. and 550°

C. and the base layer is 15 nm thick.

30. The method of claim 23, further including repeating the steps of forming and soaking the base layer between one and five times.

31. The method of claim 23, further comprising forming a capping layer over the fill material, whereby the capping layer minimizes outdiffusion of the dopant.

32. A method of fabricating a semiconductor device comprising:

(a) forming a trench in a semiconductor substrate, the trench including sidewalls defining a trench depth and a top opening defining a trench width, the sidewalls being substantially covered by a dielectric material;

(b) forming a first fill material including a light dopant over the dielectric material in a lower region of the trench;

(c) forming a second fill material including a heavy dopant in an upper region of the trench, wherein the second fill material reduces diffusion of the light dopant out of the trench, and the combination of the first and second fill materials has a resistivity of below about 5000 μ

Ω

·

cm.

33. The method according to claim 32, wherein:

forming the first fill material includes flowing a first base gas and a first dopant gas together over the trench at a first selected temperature and pressure, the first base gas including a first base material and the first dopant gas including the light dopant, wherein flowing the first base gas and the first dopant gas together facilitates in situ doping of the first base material; and

forming the second fill material includes flowing a second base gas and a second dopant gas together over the trench at a second selected temperature and pressure, the second base gas including a second base material and the second dopant gas including the heavy dopant, wherein flowing the second base gas and the second dopant gas together facilitates in situ doping of the second base material.

34. The method according to claim 32, wherein:

forming the first fill material includes depositing a first base layer on the dielectric material and soaking the first base layer with a first dopant gas containing the light dopant at a first selected temperature and pressure until the first base layer is coated with the light dopant; and

forming the second fill material includes depositing a second base layer over the first fill material and soaking the second base layer with a second dopant gas containing the heavy dopant at a second selected temperature and pressure until the second base layer is coated with the heavy dopant.

35. The method according to claim 32, wherein:

forming the first fill material includes depositing a first base layer on the dielectric material and diffusing the light dopant into the first base layer at a first selected temperature and pressure; and

forming the second fill material includes depositing a second base layer over the first fill material and diffusing the heaving dopant into the second base layer at a second selected temperature and pressure.

36. The method according to claim 32, further including:

forming a capping layer over the second fill material; and

annealing the semiconductor substrate to diffuse the light and heavy dopants.

37. The method according to claim 32, wherein the light dopant comprises P and the heavy dopant comprises As.

38. The method according to claim 32, wherein the light dopant comprises P and the heavy dopant comprises Sb.