Top layers of metal for high performance IC's
First Claim
Patent Images
1. A method for forming a top metallization system for high performance integrated circuits, comprising:
- providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines;
depositing a polymer insulating, separating layer over said semiconductor substrate;
forming openings through said polymer insulating, separating layer to expose upper metal portions of said interconnecting metallization structure;
forming said top metallization system in said openings and over said polymer insulating, separating layer, connected to said interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, having a width substantially greater than said first metal lines.
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
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Citations
42 Claims
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1. A method for forming a top metallization system for high performance integrated circuits, comprising:
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providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines;
depositing a polymer insulating, separating layer over said semiconductor substrate;
forming openings through said polymer insulating, separating layer to expose upper metal portions of said interconnecting metallization structure;
forming said top metallization system in said openings and over said polymer insulating, separating layer, connected to said interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, having a width substantially greater than said first metal lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 25)
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9. A method for forming a top metallization system for high performance integrated circuits, comprising:
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providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of fine-wire metal lines and with a passivation layer formed over said interconnecting fine-wire metallization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer;
forming openings through said polymer insulating, separating layer to expose upper metal portions of said overlaying interconnecting metallization structure;
forming said top metallization system in said openings and over said polymer insulating, separating layer, connected to said overlaying interconnecting metallization structure, wherein said top metallization system comprises a plurality of top wide-metal lines, in one or more layers, having a width substantially greater than said fine-wire metal lines, and wherein said top metallization system is used to establish electrical interconnects between multiple points within said fine-wire interconnects. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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26. A method for forming a top metallization system for high performance integrated circuits comprising:
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providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, wherein intermetal dielectric layers are formed between said plurality of first metal lines and having a passivation layer formed over said interconnecting metallization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than each of said intermetal dielectric layers;
forming openings through said polymer insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metallization structure; and
forming said top metallization system in said openings and over said polymer insulating, separating layer, connected to said overlaying interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, each of said top metal lines having a width substantially greater than said first metal lines. - View Dependent Claims (27, 29, 30, 31, 32, 33, 35, 36, 37, 38, 39, 40, 41, 42)
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28. A method for forming a top metallization system for high performance integrated circuits comprising:
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providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, wherein intermetal dielectric layers are formed between said plurality of first metal lines;
providing a passivation layer over said interconnecting metallization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than each of said intermetal dielectric layers;
forming openings through said polymer insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metallization structure; and
forming said top metallization system in said openings and over said polymer insulating, separating layer, connected to said overlaying interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, each of said top metal lines having a thickness substantially greater than said first metal lines.
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34. A method for forming a top metallization system for high performance integrated circuits comprising:
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providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines in one or more layers, wherein intermetal dielectric layers are formed between said plurality of first metal lines, and wherein said first metal lines are connected by first vias formed through said intermetal dielectric layers;
providing a passivation layer over said interconnecting metallization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than each of said intermetal dielectric layers;
forming openings through said polymer insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metallization structure, wherein said openings are substantially wider than said first vias in said intermetal dielectric layers; and
forming said top metallization system in said openings and over said polymer insulating, separating layer, connected to said overlaying interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers.
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Specification