Trench DMOS transistor with embedded trench schottky rectifier

• US 6,621,107 B2
• Filed: 08/23/2001
• Issued: 09/16/2003
• Est. Priority Date: 08/23/2001
• Status: Expired due to Fees

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Blanchard, Richard A., So, Koon Chong
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/938,253
• Publication Number:
  US 20030040144A1
• Time in Patent Office: 754 Days
• Field of Search: 257/155, 257/341, 257/342, 257/331, 257/330, 438/270, 438/268, 438/272
• US Class Current: 257/155
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A merged device is that comprises a plurality of MOSFET cells and a plurality of Schottky rectifier cells, as well as a method of designing and making the same. According to an embodiment of the invention, the MOSFET cells comprise: (a) a source region of first conductivity type formed within an upper portion of a semiconductor region, (b) a body region of second conductivity type formed within a middle portion of the semiconductor region, (c) a drain region of first conductivity type formed within a lower portion of the semiconductor region, and (d) a gate region provided adjacent the source region, the body region, and the drain region. The Schottky diode cells in this embodiment are disposed within a trench network and comprise a conductor portion in Schottky rectifying contact with the lower portion of the semiconductor region. At least one MOSFET cell gate region is positioned along a sidewall of the trench network and adjacent at least one Schottky diode cell in this embodiment.

Claims

1. A merged device comprising:

a plurality of MOSFET cells that comprise;

(a) a source region of first conductivity type formed within an upper portion of a semiconductor region,

(b) a body region of second conductivity type formed within a middle portion of said semiconductor region,

(c) a drain region of first conductivity type formed within a lower portion of said semiconductor region, and

(d) a gate region provided adjacent said source region, said body region, and said drain region; and

a plurality of Schottky diode cells disposed at the bottom of a trench network, wherein said Schottky diode cells comprise a conductor portion in Schottky rectifying contact with said lower portion of said semiconductor region;

wherein at least one gate region of said plurality of MOSFET cell is positioned along a sidewall of said trench network adjacent at least one Schottky diode cell.

2. The device of claim 1, wherein said gate region comprises a doped polysilicon region adjacent a silicon dioxide region.

3. The device of claim 1, wherein said first conductivity type is n-type conductivity and said second conductivity type is p-type conductivity.

4. The device of claim 3, further comprising a heavily doped contact region for contact to the body region.

5. The device of claim 3, further comprising a p-type region that is below the Schottky diode and contacts the perimeter of the Schottky diode.

6. The device of claim 1, wherein said semiconductor region is a silicon region.

7. The device of claim 6, wherein said semiconductor region is an epitaxial silicon region.

8. The device of claim 6, wherein said conductor portion in Schottky rectifying contact with said lower portion of said semiconductor region comprises one of the materials titanium-tungsten, platinum silicide, aluminum or aluminum alloy.

9. The device of claim 1, wherein at least one of said MOSFET cells is octagonal in shape.

10. A merged device comprising:

a semiconductor substrate of first conductivity type;

a semiconductor epitaxial layer disposed over said substrate;

a trench network extending into said epitaxial region from an upper surface of said epitaxial layer and forming a plurality of mesas within said device;

a plurality of MOSFET cells that comprise;

(a) a source region of said first conductivity type disposed within one of said mesas,

(b) a body region of second conductivity type disposed within said one of said mesas, said body region forming a junction with said source region,

(c) a drain region of first conductivity type at least partially disposed within said one of said mesas, said drain region forming a junction with said body region; and

(d) a gate region situated within said trench network such that it is adjacent said source region, said body region and said drain region, said gate region comprising (i) an insulating region lining at least a portion of said trench network and (ii) a conductive region within said trench network adjacent said insulating region, said conductive region being separated from said source, body and drain regions by said insulating region; and

a plurality of Schottky diode cells formed at the bottom portions of said bench network, wherein said Schottky dioide cells comprise a conductor portion that is in Schottky rectifying contact with said epitaxial layer,

wherein at least some of said gate regions of said MOSFET cells are positioned along sidewalls of said trench network adjacent said conductor portions of at least some of said Schottky diodes.

11. The device of claim 10, wherein said conductor makes ohmic contact with said source regions and said body regions.

12. The device of claim 11, wherein said conductor portion in Schottky rectifying contact with said lower portion of said semiconductor region comprises one of the materials titanium-tungsten, platinum silicide, aluminum or aluminum alloy.

13. The device of claim 10, wherein said gate region comprises a doped polysilicon region adjacent a silicon dioxide region.

14. The device of claim 10, wherein said first conductivity type is n-type conductivity and said second conductivity type is p-type conductivity.

15. The device of claim 14, further comprising a heavily doped contact region for contact to the body region.

16. The device of claim 14, further comprising a p-type region that is below the Schottky diode and contacts the perimeter of the Schottky diode.

17. The device of claim 10, wherein said semiconductor is silicon.

18. The device of claim 10, wherein at least some of said MOSFET cells and at least some of said Schottky diode cells are arranged in a geometric configuration selected from a group consisting of an in-line square geometry, an offset square geometry, and a hexagonal geometry.

19. The device of claim 10, wherein at least some of said MOSFET cells are octagonal cells.

20. The device of claim 10, wherein at least some of said MOSFET cells and at least some of said Schottky diode cells are arranged in a geometry comprising alternating first and second cell rows, wherein the cells of said first cell rows are greater in area than the cells of said second cell rows, and wherein said cells of said first cell rows are octagonal cells.

21. The device of claim 20, wherein said cells of said first cell rows are regular octagons.

22. The device of claim 20, wherein said MOSFET cells are positioned within said first cell rows and said Schottky diode cells are positioned within said second cell rows.

23. The device of claim 20, wherein said cells of said second cell rows are octagonal cells or square cells.

24. A merged device comprising Schottky diode cells and MOSFET cells, wherein said Schottky diode cells are located at the bottom of a trench network, wherein said Schottky diode cells comprise a gate conductor portion in Schottky rectifying contact at the bottom of the trench network, and wherein a portion of the gate conductive region and a portion of a gate insulation region of said MOSFET cells are provided on sidewalls of said trench network surrounding each Schottky rectifying contact.

25. A method of forming a merged device comprising:

forming a plurality of Schottky diode cells; and

forming a plurality of MOSFET cells,

wherein said Schottky diode cells are located at the bottom of a trench network, wherein gate regions of said MOSFET cells comprise a conductive region and an insulating region, wherein a portion of the sate conductive region and a portion of the gate insulation regions are provided on sidewalk of said trench network surrounding each Schottky rectifying contact, the Schottky rectifying contact located at the bottom of the trench network, and

wherein said conductive region of said gate regions is formed without the aid of a masking layer.

26. The method of claim 25, wherein said gate conductive region is formed by etching a doped polysilicon layer in an anisotropic etching process.