Reconfigurable priority encoding

• US 6,621,295 B1
• Filed: 01/15/2002
• Issued: 09/16/2003
• Est. Priority Date: 01/15/2002
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: James-Roxby, Philip B., Downs, Daniel J.
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US10/047,667
• Time in Patent Office: 609 Days
• Field of Search: 326/37, 326/38, 326/39, 326/40, 326/41, 326/105, 341/50, 714/724, 714/725, 711/108, 711/158
• US Class Current: 326/38
• CPC Class Codes: G06F 7/74 Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders with shifting G06F5/01

Abstract

A reconfigurable priority encoding arrangement and method. In various embodiments, the invention identifies, from a plurality of input signals, a highest priority signal that is in a selected state. A priority routing block is implemented on a programmable logic device (PLD). The routing block has a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports. A priority encoder is also implemented on the PLD and has input ports respectively coupled to the output ports of the priority routing block. Each input port has a priority relative to others of the input ports. The priority encoder is configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state.

Claims

1. A priority encoding arrangement for identifying a highest priority signal in a selected state from a plurality of input signals, comprising:

a priority routing block implemented on a programmable logic device (PLD), the priority routing block having a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports; and

a priority encoder implemented on the PLD and having input ports respectively coupled to the output ports of the priority routing block, wherein each input port has a priority relative to others of the input ports, the priority encoder configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state,

wherein the PLD is configured with a current configuration bitstream and further comprising a run-time reconfiguration control arrangement coupled to the programmable logic device, the run-time reconfiguration control arrangement configured to generate from the current configuration bitstream a new configuration bitstream that changes one or more selected couplings of routing block input ports to routing block output ports and reconfigure the PLD with the new configuration bitstream.

2. The priority encoding arrangement of claim 1, wherein the run-time reconfiguration control arrangement is further configured to partially reconfigure the PLD with the new configuration bitstream without disabling during reconfiguration ports of the priority routing block and priority encoder that are not affected by the new configuration bitstream.

3. The priority encoding arrangement of claim 1, further comprising a plurality of match units respectively coupled to the input ports of the routing block, each match unit configured to generate a hit signal in response to a match between an input data set and a configured data set.

4. The priority encoding arrangement of claim 3, wherein the run-time reconfiguration control arrangement is further configured to generate a configuration bitstream that implements an additional match unit and connects the additional match unit to the routing block.

5. The priority encoding arrangement of claim 3, wherein the run-time reconfiguration control arrangement is further configured to generate a configuration bitstream that disconnects a selected match unit from the routing block.

6. The priority encoding arrangement of claim 3, wherein the run-time reconfiguration control arrangement is further configured to generate a configuration bitstream that changes a priority associated with a match unit by reassignment of input ports to output ports in the routing block.

7. A method for run-time reconfigurable identification of a highest priority signal in a selected state from a plurality of input signals, comprising:

configuring a programmable logic device (PLD) with a current configuration bitstream that implements,

a priority routing block having input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports; and

a priority encoder having input ports respectively coupled to the output ports of the priority routing block, wherein each input port has a priority relative to others of the input ports and the priority encoder is configured to generate an address signal that identifies the input signal of a highest priority and that is in the selected state;

generating from the current configuration bitstream a new configuration bitstream that changes one or more selected couplings of routing block input ports to routing block output ports; and

reconfiguring the PLD with the new configuration bitstream.

8. The method of claim 7, further comprising partially reconfiguring the PLD with the new configuration bitstream.

9. The method of claim 7, wherein the current configuration bitstream implements a plurality of match units respectively coupled to the input ports of the routing block, each match unit configured to generate a hit signal in response to a match between an input data set and a configured data set.

10. The method of claim 9, further comprising generating in the new configuration bitstream configuration data that implement an additional match unit and connect the additional match unit to the routing block.

11. The method of claim 9, further comprising generating in the new configuration bitstream configuration data that disconnect a selected match unit from the routing block.

12. The method of claim 9, generating in the new configuration bitstream configuration data that change a priority associated with a match unit by reassignment of input ports to output ports in the routing block.

13. An apparatus for run-time reconfigurable identification of a highest priority signal in a selected state from a plurality of input signals, comprising:

means for configuring a programmable logic device (PLD) with a current configuration bitstream that implements a priority routing block having input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports, the current configuration bitstream further implementing a priority encoder having input ports respectively coupled to the output ports of the priority routing block, wherein each input port has a priority relative to others of the input ports and the priority encoder is configured to generate an address signal that identifies the input signal of a highest priority and that is in the selected state;

means for generating from the current configuration bitstream a new configuration bitstream that changes one or more selected couplings of routing block input ports to routing block output ports; and

means for reconfiguring the PLD with the new configuration bitstream.