Reconfigurable priority encoding
First Claim
1. A priority encoding arrangement for identifying a highest priority signal in a selected state from a plurality of input signals, comprising:
- a priority routing block implemented on a programmable logic device (PLD), the priority routing block having a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports; and
a priority encoder implemented on the PLD and having input ports respectively coupled to the output ports of the priority routing block, wherein each input port has a priority relative to others of the input ports, the priority encoder configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state, wherein the PLD is configured with a current configuration bitstream and further comprising a run-time reconfiguration control arrangement coupled to the programmable logic device, the run-time reconfiguration control arrangement configured to generate from the current configuration bitstream a new configuration bitstream that changes one or more selected couplings of routing block input ports to routing block output ports and reconfigure the PLD with the new configuration bitstream.
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Accused Products
Abstract
A reconfigurable priority encoding arrangement and method. In various embodiments, the invention identifies, from a plurality of input signals, a highest priority signal that is in a selected state. A priority routing block is implemented on a programmable logic device (PLD). The routing block has a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports. A priority encoder is also implemented on the PLD and has input ports respectively coupled to the output ports of the priority routing block. Each input port has a priority relative to others of the input ports. The priority encoder is configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state.
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Citations
13 Claims
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1. A priority encoding arrangement for identifying a highest priority signal in a selected state from a plurality of input signals, comprising:
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a priority routing block implemented on a programmable logic device (PLD), the priority routing block having a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports; and
a priority encoder implemented on the PLD and having input ports respectively coupled to the output ports of the priority routing block, wherein each input port has a priority relative to others of the input ports, the priority encoder configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state, wherein the PLD is configured with a current configuration bitstream and further comprising a run-time reconfiguration control arrangement coupled to the programmable logic device, the run-time reconfiguration control arrangement configured to generate from the current configuration bitstream a new configuration bitstream that changes one or more selected couplings of routing block input ports to routing block output ports and reconfigure the PLD with the new configuration bitstream. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for run-time reconfigurable identification of a highest priority signal in a selected state from a plurality of input signals, comprising:
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configuring a programmable logic device (PLD) with a current configuration bitstream that implements, a priority routing block having input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports; and
a priority encoder having input ports respectively coupled to the output ports of the priority routing block, wherein each input port has a priority relative to others of the input ports and the priority encoder is configured to generate an address signal that identifies the input signal of a highest priority and that is in the selected state;
generating from the current configuration bitstream a new configuration bitstream that changes one or more selected couplings of routing block input ports to routing block output ports; and
reconfiguring the PLD with the new configuration bitstream. - View Dependent Claims (8, 9, 10, 11, 12)
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13. An apparatus for run-time reconfigurable identification of a highest priority signal in a selected state from a plurality of input signals, comprising:
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means for configuring a programmable logic device (PLD) with a current configuration bitstream that implements a priority routing block having input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports, the current configuration bitstream further implementing a priority encoder having input ports respectively coupled to the output ports of the priority routing block, wherein each input port has a priority relative to others of the input ports and the priority encoder is configured to generate an address signal that identifies the input signal of a highest priority and that is in the selected state;
means for generating from the current configuration bitstream a new configuration bitstream that changes one or more selected couplings of routing block input ports to routing block output ports; and
means for reconfiguring the PLD with the new configuration bitstream.
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Specification