Phase-locked loop with short transient recovery duration and small interference signal component

• US 6,621,356 B2
• Filed: 03/27/2002
• Issued: 09/16/2003
• Est. Priority Date: 09/27/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Schönleber, Günter, Memmler, Bernd, Götz, Edmund
• Primary Examiner(s): Kinkead, Arnold
• Application Number:
  US10/113,632
• Publication Number:
  US 20020153959A1
• Time in Patent Office: 538 Days
• Field of Search: 331/DIG.2, 331/17, 331/1.A, 331/18, 331/34, 331/25, 331/16, 327/156, 327/159
• US Class Current: 331/25
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/1972 for reducing the locking time interval H03L7/1974, H03L7/199 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

In order to shorten the transient recovery duration, the phase-locked loop has a voltage-controlled oscillator providing an oscillator signal to a first frequency divider. The first frequency divider divides the frequency of the oscillator signal, generates a first divider output signal therefrom, and passes it to a phase comparator during the transient recovery duration of the phase-locked loop. Furthermore, a unit is provided, which, after the transient recovery duration of the phase-looped loop, divides the frequency of the first divider output signal and passes it to the phase comparator. The phase comparator compares the first divider output signal with a first reference signal during the transient recovery duration. The phase comparator compares the divided divider output signal with a second reference signal after the transient recovery duration. The output of the phase comparator is connected to the voltage-controlled oscillator via a controllable charge pump.

Claims

1. A phase-locked loop, comprising:

a voltage-controlled oscillator for generating an oscillator signal having a frequency;

a controllable charge pump having an output connected to said voltage-controlled oscillator;

a phase comparator having an output connected to said controllable charge pump;

a first frequency divider which, during a transient recovery duration, generates a first divider output signal by dividing the frequency of the oscillator signal and provides the first divider output signal to said phase comparator, the first divider output signal having a frequency;

a unit which, after the transient recovery duration, divides the frequency of the first divider output signal to obtain a divided first divider output signal and provides the divided first divider output signal to said phase comparator; and

an accumulator for holding a value, said first frequency divider connected to said accumulator;

said first frequency divider depending on the value held in said accumulator, dividing the frequency of the oscillator signal by a value selected from the group consisting of a first value and a second value;

said phase comparator comparing the first divider output signal with a first reference signal during the transient recovery duration; and

said phase comparator comparing the divided first divider output signal with a second reference signal after the transient recovery duration.

2. The phase-locked loop according to claim 1, wherein:

said unit includes a second frequency divider and a first multiplexer with a first input, a second input, and an output;

said first frequency divider has an output connected to said first input of said first multiplexer; and

said second frequency divider has an output connected to said second input of said first multiplexer.

3. The phase-locked loop according to claim 2, comprising:

a third frequency divider for receiving a reference oscillator signal from a reference oscillator and for generating the first reference signal from the reference oscillator signal; and

a fourth frequency divider for receiving the reference oscillator signal from the reference oscillator and for generating the second reference signal from the reference oscillator signal.

4. The phase-locked loop according to claim 2, comprising:

a second multiplexer that selectively passes a reference signal selected from the group consisting of the first reference signal and the second reference signal to said phase comparator.

5. The phase-locked loop according to claim 2, comprising:

a second multiplexer having a first input and a second input;

a third frequency divider connected to said first input of said second multiplexer; and

a fourth frequency divider connecting said third frequency divider to said second input of said second multiplexer.

6. The phase-locked loop according to claim 1, comprising:

a filter connected between said controllable charge pump and said voltage-controlled oscillator.

7. The phase-locked loop according to claim 6, wherein said filter is a low-pass filter.

8. The phase-locked loop according to claim 1, comprising:

a control device;

said unit including a multiplexer that is controlled by said control device.

9. The phase-locked loop according to claim 8, comprising:

a filter connected between said controllable charge pump and said voltage-controlled oscillator;

said charge pump and said filter having parameters that are prescribed by said control device.

10. The phase-locked loop according to claim 1, wherein:

said unit has a first gating circuit for gating the first divider output signal from said first frequency divider; and

said unit has a gating logic control circuit for controlling said first gating circuit.

11. The phase-locked loop according to claim 10, wherein:

said first gating circuit is an AND gate that has a first input and a second input;

said first frequency divider has an output connected to said first input of said AND gate;

said gating logic control circuit has an output connected to said second input of said AND gate; and

said AND gate has an output connected to said phase comparator.

12. The phase-locked loop according to claim 11, comprising:

a second gating circuit for gating a reference signal;

said gating logic control circuit controlling said second gating circuit.

13. The phase-locked loop according to claim 10, comprising:

a second gating circuit for gating a reference signal;

said gating logic control circuit controlling said second gating circuit.

14. The phase-locked loop according to claim 13, comprising:

a control device that, together with the reference signal, controls said gating logic control circuit.

15. The phase-locked loop according to claim 1, wherein the phase-locked loop operates in a fractional-N mode during the transient recovery duration and in an integer-N mode in a settled state.