Micro electromechanical switch having self-aligned spacers

• US 6,621,392 B1
• Filed: 04/25/2002
• Issued: 09/16/2003
• Est. Priority Date: 04/25/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Stein, Kenneth J., Petrarca, Kevin S., Volant, Richard P., Angell, David, Wille, William C., Canaperi, Donald F., Kocis, Joseph T.
• Primary Examiner(s): DONOVAN, LINCOLN D
• Application Number:
  US10/132,743
• Time in Patent Office: 509 Days
• Field of Search: 438/48-49, 438/52, 257/414, 257/421, 335/78, 200/181, 361/233, 361/277-281
• US Class Current: 335/78
• CPC Class Codes: B81B 2201/014 having a cantilever fixed on one side connected to one or more dimples
• CPC Class Codes: B81B 3/001 Structures having a reduced contact area, e.g. with bumps or with a textured surface
• CPC Class Codes: H01H 2059/0072 with stoppers or protrusions for maintaining a gap, reducing the contact area or for preventing stiction between the movable and the fixed electrode in the attracted position
• CPC Class Codes: H01H 59/0009 making use of micromechanics

Abstract

A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.

Claims

1. A method of forming a micro-electromechanical switch (MEMS) comprising the steps of:

a) depositing a first dielectric layer on a substrate, said first dielectric layer having a plurality of conductive interconnect lines formed therein;

b) wet etching metal to form trenches on the boundaries of said conductive interconnect lines;

c) depositing a second dielectric layer through which conductive vias are formed, said conductive vias contacting at least one of said plurality of conductive interconnect lines and replicating the trench topographies to the top surface of said second dielectric layer and filling with metal said replicated trench topographies;

d) forming a cavity that is etched-out from said second dielectric layer and having said metal trench topographies selectively inhibit etching the dielectric underneath the metal trench topographies to form self-aligned spacers;

e) filling said cavity with sacrificial material and planarizing said sacrificial material; and

f) depositing a third dielectric layer to form a conductive beam with said conductive vias contacting said conductive beam.

2. The method as recited in claim 1, wherein said second dielectric layer conforms to said first dielectric layer and to said conductive interconnect lines.

3. The method as recited in claim 1, wherein said self-aligned spacers have a width ranging from 2000 Å

to 1.5 μ

m. and a height ranging from 2000 Å

to 2 μ

m.

4. The method as recited in claim 1, wherein said self-aligned spacers are made of a material that is selected from the group consisting of SiO2, Si3N4 and SiCOH.

5. The method as recited in claim 1, wherein said metal trench topographies are made of copper or of any other platable conductive material.

6. The method as recited in claim 1, wherein step a) further comprises selectively masking said plurality of conductive lines to provide pillars formed within said conductive material to create additional boundaries for placing additional spacers within the perimeter defined by the top surface of said conductive interconnect lines.

7. The method as recited in claim 1, wherein the metal on the surface of said interconnect conductive lines is compatible with the mask RIE'"'"'ing.

8. The method as recited in claim 7, wherein metal is left in the replicated trench topographies on the top surface of said second dielectric layer.

9. The method as recited in claim 1, wherein said MEMS device is a capacitive switch wherein the capacitance is partially determined by the height of said self-aligned spacer.

10. The method as recited in claim 1, wherein said capacitive MEMS device is a customizable MEM switch.

11. A micro-electromechanical switch (MEMS) comprising:

a) a first dielectric layer on a substrate, said first dielectric layer having a plurality of conductive interconnect lines formed therein;

b) trenches formed on the boundaries of said conductive interconnect lines;

c) a second dielectric layer through which conductive vias are formed, said conductive vias contacting at least one of said plurality of conductive interconnect lines and trench topographies replicated on the top surface of said second dielectric layer, said trench topographies being filled with metal;

d) a cavity etched-out from said second dielectric layer wherein said metal filled trench topographies selectively inhibit etching the dielectric underneath the metal trench topographies to form self-aligned spacers, said cavity being filled with sacrificial material and planarized; and

e) a third dielectric layer with a conductive beam formed therein and contacting said conductive vias.

12. The MEM switch as recited in claim 11, wherein said second dielectric layer conforms to said first dielectric layer and to said conductive interconnect lines.

13. The MEM switch as recited in claim 11, wherein said self-aligned spacers have a width ranging from 2000 Å

to 1.5 μ

m. and a height ranging from 2000 Å

to 2 μ

m.

14. The MEM switch as recited in claim 11, wherein said self-aligned spacers are made of a material that is selected from the group consisting of SiO2, Si3N4 and SiCOH.

15. The MEM switch as recited in claim 11, wherein said trenches formed on the boundaries of said conductive interconnect lines are filled with copper or any other platable conductive material.

16. The MEM switch as recited in claim 11, wherein step a) further comprises selectively masking said plurality of conductive lines to provide pillars formed within said conductive material to create additional boundaries for placing additional spacers within the perimeter defined by the top surface of said conductive interconnect lines.

17. The MEM switch as recited in claim 11, wherein said metal is compatible with mask RIE'"'"'ing.

18. The MEM switch as recited in claim 17, wherein metal is left in the replicated trench topographies on the top surface of said second dielectric layer.

19. The MEM switch as recited in claim 11, wherein said MEMS device is a capacitive switch wherein the capacitance is partially determined by the height of said self-aligned spacer.

20. The MEM switch as recited in claim 11, wherein said capacitive MEMS device is a customizable MEM switch.