System and method to reduce phase modulation bandwidth

• US 6,621,876 B2
• Filed: 03/01/2001
• Issued: 09/16/2003
• Est. Priority Date: 03/01/2001
• Status: Expired due to Term

• Current Assignee: Optis Wireless Technology, LLC (Brevet Capital)
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Camp, William O. Jr., Isberg, Martin
• Primary Examiner(s): Le, Amanda T.
• Application Number:
  US09/797,346
• Publication Number:
  US 20020122467A1
• Time in Patent Office: 929 Days
• Field of Search: 375/146, 375/271, 375/278, 375/279, 375/284, 375/285, 375/290, 375/296, 375/297, 375/302, 375/308, 332/103, 332/144, 332/123, 455/42, 455/110
• US Class Current: 375/296
• CPC Class Codes: H04L 27/367 using predistortion

Abstract

A signal source generates a phase-modulated output signal responsive to a phase-modulation signal. A phase splitter splits the phase-modulated output signal into two or more phase-offset output signals. A switch provides a selected one of the phase-offset output signals from the phase splitter to a transmit amplifier circuit. Large phase transitions in the phase-modulation signal are detected and reduced to decrease modulation bandwidth requirements at the signal source. When a phase transition in the phase-modulation signal is reduced, the switch is coherently switched from one phase-offset output signal to another to substantially restore the full phase transition in the output signal presented to the transmit amplifier circuit. In this manner, the transmit amplifier receives substantially the same phase transitions as are in the original phase-modulation signal.

Claims

1. A phase modulation circuit comprising:

a signal source receiving a modified phase information signal at an input and generating a phase-modulated output signal at an output;

a phase reducer to selectively reduce the magnitude of phase transitions in a phase information signal to generate said modified phase information signal with reduced phase transitions at said input of said signal source; and

a phase restorer responsive to a signal from said phase reducer to restore the magnitude of said reduced phase transitions in said phase-modulated output signal.

2. The phase modulation circuit of claim 1 wherein said phase reducer comprises:

a detection circuit to detect phase transitions in said phase information signal that exceed at least one predefined limit; and

an adjustment circuit responsive to a signal from said detection circuit to reduce the magnitude of said phase transitions in said phase information signal that exceed said at least one predefined limit.

3. The phase modulation circuit of claim 2 wherein said phase reducer further comprises an input buffer to sequentially buffer incoming samples of said phase information signal, and further wherein said input buffer is communicatively coupled to said detection circuit.

4. The phase modulation circuit of claim 3 wherein said detection circuit further comprises a controller to examine said incoming samples of said phase information signal held in said input buffer to identify phase transitions in said phase information signal that exceed said at least one predefined limit.

5. The phase modulation circuit of claim 2 wherein said adjustment circuit comprises logic to subtract a defined amount of phase transition from selected samples of said phase information signal.

6. The phase modulation circuit of claim 2 wherein said detection circuit comprises a zero-crossing detector to detect phase transitions in said phase information signal within a defined range of 180°

by identifying amplitude minimums in an amplitude information signal coherently generated in association with said phase information signal.

7. The phase modulation circuit of claim 1 wherein said phase information signal is a digital signal containing successive phase value samples corresponding to a desired sequence of transmit symbols, and further wherein said phase reducer comprises:

an input buffer to delay incoming samples of said phase information signal;

a controller to read said input buffer and to generate a control signal when said input buffer contains samples corresponding to a phase transition that exceeds a defined threshold; and

a phase adjustment circuit to receive delayed samples of said phase information signal from said input buffer, and, responsive to said control signal, to operate on selected samples corresponding to said phase transition that exceeds said defined threshold to reduce the magnitude of said phase transition by a defined amount.

8. The phase modulation circuit of claim 1 wherein said phase restorer comprises:

a phase splitter to generate at least one phase-offset signal based on phase-shifting said phase-modulated output signal from said signal source by a desired amount; and

a selection switch responsive to said signal from said phase reducer to couple a selected one of said phase-modulated output signal and said at least one phase-offset signal to a phase-modulation input of a transmit amplifier.

9. The phase modulation circuit of claim 8 wherein said phase splitter comprises at least one phase shifter to impart said desired amount of phase shift to said phase-modulated output signal.

10. The phase modulation circuit of claim 8 wherein said phase splitter comprises a plurality of phase shifters each imparting a different desired amount of phase shift to said phase-modulated output signal, such that each said phase-offset signal has a different phase-offset with respect to said phase modulation signal.

11. The phase modulation circuit of claim 10 wherein said selection switch comprises a multiplexer with a set of inputs to receive said phase-modulated output signal and said plurality of phase-offset signals, and an output to selectively couple one of said inputs to said transmit amplifier based on said control signal.

12. The phase modulation circuit of claim 1 wherein said phase reducer comprises a portion of a digital signal processor.

13. The phase modulation circuit of claim 1 wherein said signal source comprises a phase-locked loop circuit modulating a carrier frequency signal responsive to said phase information signal.

14. The phase modulation circuit of claim 1 further comprising a baseband processor receiving input data and generating said phase information signal based on said digital data and a defined modulation scheme.

15. The phase modulation circuit of claim 14 wherein said baseband processor and said phase reducer comprise a digital signal processor.

16. A RF transmitter comprising:

a baseband processor to generate a phase information signal based on input data and a defined modulation scheme;

a phase modulation circuit comprising;

a signal source receiving a modified phase information signal at an input and generating a phase-modulated output signal at an output;

a phase reducer to selectively reduce the magnitude of phase transitions in a phase information signal to generate said modified phase information signal with reduced phase transitions at said input of said signal source; and

a phase restorer responsive to a signal from said phase reducer to restore the magnitude of said reduced phase transitions in said phase-modulated output signal; and

a transmit amplifier with a phase-modulation input coupled to said phase restorer to receive said phase-modulated output signal with restored phase transition magnitudes as a first input signal, said transmit amplifier generating a transmit signal responsive to said first input signal.

17. The RF transmitter of claim 16 wherein said baseband processor generates an amplitude information signal in conjunction with said phase information signal based on said input data and said modulation scheme, and further wherein said transmit amplifier further comprises an amplitude-modulation input to receive said amplitude information signal as a second input signal, said transmit amplifier generating said transmit signal responsive to said second input signal.

18. The RF transmitter of claim 17 wherein a phase modulation signal path delay exists between said transmit amplifier and said baseband processor arising from said phase modulation circuit, and further comprising a compensating delay element in an amplitude modulation signal path between said transmit amplifier and said baseband processor.

19. The RF transmitter of claim 16 wherein said phase reducer comprises:

a detection circuit to detect phase transitions in said phase information signal that exceed at least one predefined limit; and

an adjustment circuit responsive to a signal from said detection circuit to reduce the magnitude of said phase transitions in said phase information signal that exceed said at least one predefined limit.

20. The RF transmitter of claim 19 wherein said phase reducer further comprises an input buffer to sequentially buffer incoming samples of said phase information signal, and further wherein said input buffer is communicatively coupled to said detection circuit.

21. The RF transmitter of claim 20 wherein said detection circuit further comprises a controller to examine said incoming samples of said phase information signal held in said input buffer to identify said phase transitions in said phase information signal that exceed said at least one predefined limit.

22. The RF transmitter of claim 19 wherein said adjustment circuit comprises logic to subtract a defined amount of phase transition from selected samples of said phase information signal.

23. The RF transmitter of claim 16 wherein said phase information signal is a digital signal containing successive phase value samples corresponding to a desired sequence of transmit symbols, and further wherein said phase reducer comprises:

an input buffer to delay incoming samples of said phase information signal;

a controller to read said input buffer and to generate a control signal when said input buffer contains samples corresponding to a phase transition that exceeds a defined threshold; and

a phase adjustment circuit to receive delayed samples of said phase information signal from said input buffer, and, responsive to said control signal, to operate on selected samples corresponding to said phase transition that exceeds said defined threshold to reduce the magnitude of said phase transition by a defined amount.

24. The RF transmitter of claim 16 wherein said phase restorer comprises:

a phase splitter to generate at least one phase-offset signal based on phase-shifting said phase-modulated output signal from said signal source by a desired amount; and

a selection switch responsive to said signal from said phase reducer to couple a selected one of said phase-modulated output signal and said at least one phase-offset signal to a phase-modulation input of a transmit amplifier.

25. A method of reducing phase-modulation bandwidth at a signal source, the method comprising:

identifying phase value transitions in a phase information signal that exceed a predefined limit, said phase information signal corresponding to a desired sequence of transmit symbols;

reducing said identified phase value transitions in said phase information signal to lower the modulation bandwidth of said phase information signal;

modulating said signal source with said phase information signal to generate a phase-modulated output signal, said phase-modulated output signal including reduced phase transitions corresponding to said identified phase transitions that were reduced in said phase information signal; and

restoring said reduced phase transitions in said phase-modulated output signal to counter the effects of lowering said modulation bandwidth of said phase information signal.

26. The method of claim 25 wherein reducing said identified phase value transitions in said phase information signal to lower the modulation bandwidth of said phase information signal comprises:

for a given one of said identified phase transitions, determining an amount by which to reduce said given one of said identified phase transitions based on an actual magnitude of said given one of said identified phase transitions; and

reducing said actual magnitude by said determined amount.

27. The method of claim 26 wherein determining an amount by which to reduce said given one of said identified phase transitions based on an actual magnitude of said given one of said identified phase transitions comprises:

identifying one of a set of fixed magnitude values nearest to said actual magnitude; and

subtracting said identified one of said set of fixed magnitude values from said actual magnitude.

28. The method of claim 26 wherein restoring said reduced phase transitions in said phase-modulated output signal to offset the effects of lowering said modulation bandwidth of said phase information signal comprises, for a given one of said reduced phase transitions in said phase-modulated output signal, restoring an amount of phase transition substantially equal to said amount by which the corresponding one of said identified phase transitions in said phase information signal was reduced.

29. The method of claim 25 wherein restoring said reduced phase transitions in said phase-modulated output signal to offset the effects of lowering said modulation bandwidth of said phase information signal comprises:

identifying phase transitions in said phase-modulated output signal that correspond with said identified phase transitions in said phase information signal that were reduced; and

adding back to each said identified phase transition in said phase-modulated output signal an amount of phase transition magnitude substantially equal to the amount by which the corresponding one of said identified phase transitions in said phase information signal was reduced.

30. The method of claim 29 wherein adding back to each said identified phase transition in said phase-modulated output signal an amount of phase transition magnitude substantially equal to the amount by which the corresponding one of said identified phase transitions in said phase information signal was reduced comprises:

generating at least one phase-offset signal at a known phase offset by phase-shifting said phase-modulated output signal; and

switching between said phase-modulated output signal and said at least one phase-offset signal to impart phase transitions in a switched phase-modulated output signal equal to said amount of phase transition magnitude to be added back to each said identified phase transition.