Automated process monitoring and analysis system for semiconductor processing

• US 6,622,059 B1
• Filed: 04/13/2000
• Issued: 09/16/2003
• Est. Priority Date: 04/13/2000
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Miller, Michael L., Toprac, Anthony John
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): RODRIGUEZ, PAUL L
• Application Number:
  US09/548,779
• Time in Patent Office: 1,251 Days
• Field of Search: 438/5, 438/10, 438/11, 438/17, 438/18, 700/121, 700/95, 700/96, 700/108, 700/109, 700/110, 700/117-120, 700/29-31
• US Class Current: 700/121
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method is provided for manufacturing, the method comprising processing a workpiece, measuring a parameter characteristic of the processing, and forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a transistor model. The method also comprises predicting a wafer electrical test (WET) resulting value based on the output signal, detecting faulty processing based on the predicted WET resulting value, and correcting the faulty processing.

Claims

1. A method of manufacturing, the method comprising:

processing a workpiece;

measuring a parameter characteristic of the processing;

forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model;

predicting a wafer electrical test (WET) resulting value based on the output signal;

detecting faulty processing based on the predicted WET resulting value; and

correcting the faulty processing.

2. The method of claim 1, wherein using the characteristic parameter measured as the input to the partial least squares transistor model comprises using the partial least squares transistor model to map a set of in-line process metrology input values to a set of WET measurement output values.

3. The method of claim 2, wherein using the partial least squares transistor model to map the set of the in-line process metrology input values to the set of the WET measurement output values comprises using the partial least squares transistor model to define at least a subset of the in-line process metrology input values having a significant effect on at least a subset of the WET measurement output values.

4. The method of claim 3, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

5. The method of claim 4, wherein inverting the transistor model to define the change in the processing comprises defining a change in a critical dimension of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.

6. The method of claim 5, wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line width and a spacer width of an MOS transistor.

7. The method of claim 5, wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line thickness, a gate dielectric thickness and a silicide layer thickness of an MOS transistor.

8. The method of claim 4, wherein inverting the transistor model to define the change in the processing comprises defining a change in a doping level of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.

9. The method of claim 8, wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain region of an MOS transistor.

10. The method of claim 8, wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain extension (SDE) region of an MOS transistor.

11. The method of claim 2, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

12. The method of claim 11, wherein inverting the transistor model to define the change in the processing comprises defining a change in a critical dimension of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.

13. The method of claim 12, wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line width and a spacer width of an MOS transistor.

14. The method of claim 12, wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line thickness, a gate dielectric thickness and a silicide layer thickness of an MOS transistor.

15. The method of claim 11, wherein inverting the transistor model to define the change in the processing comprises defining a change in a doping level of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.

16. The method of claim 15, wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain region of an MOS transistor.

17. The method of claim 15, wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain extension (SDE) region of an MOS transistor.

18. The method of claim 1, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

19. The method of claim 18, wherein inverting the transistor model to define the change in the processing comprises defining a change in a critical dimension of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.

20. The method of claim 19, wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line width and a spacer width of an MOS transistor.

21. The method of claim 19, wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line thickness, a gate dielectric thickness and a silicide layer thickness of an MOS transistor.

22. The method of claim 18, wherein inverting the transistor model to define the change in the processing comprises defining a change in a doping level of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.

23. The method of claim 22, wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain region of an MOS transistor.

24. The method of claim 22, wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain extension (SDE) region of an MOS transistor.

25. A computer-readable, program storage device encoded with instructions that, when executed by a computer, perform a method for manufacturing a workpiece, the method comprising:

processing the workpiece;

measuring a parameter characteristic of the processing performed on the workpiece;

forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model;

predicting a wafer electrical test (WET) resulting value based on the output signal;

detecting faulty processing based on the predicted WET resulting value; and

correcting the faulty processing.

26. The computer-readable, program storage device of claim 25, wherein using the characteristic parameter measured as the input to the partial least squares transistor model comprises using the partial least squares transistor model to map a set of in-line process metrology input values to a set of WET measurement output values.

27. The computer-readable, program storage device of claim 26, wherein using the partial least squares transistor model to map the set of the in-line process metrology input values to the set of the WET measurement output values comprises using the partial least squares transistor model to define at least a subset of the in-line process metrology input values having a significant effect on at least a subset of the WET measurement output values.

28. The computer-readable, program storage device of claim 27, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

29. The computer-readable, program storage device of claim 26, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

30. The computer-readable, program storage device of claim 25, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

31. A computer programmed to perform a method of manufacturing, the method comprising:

processing a workpiece;

measuring a parameter characteristic of the processing performed on the workpiece;

forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model;

predicting a wafer electrical test (WET) resulting value based on the output signal;

detecting faulty processing based on the predicted WET resulting value; and

correcting the faulty processing.

32. The computer of claim 31, wherein using the characteristic parameter measured as the input to the partial least squares transistor model comprises using the partial least squares transistor model to map a set of in-line process metrology input values to a set of WET measurement output values.

33. The computer of claim 32, wherein using the partial least squares transistor model to map the set of the in-line process metrology input values to the set of the WET measurement output values comprises using the partial least squares transistor model to define at least a subset of the in-line process metrology input values having a significant effect on at least a subset of the WET measurement output values.

34. The computer of claim 33, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

35. The computer of claim 32, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

36. The computer of claim 31, wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.

37. A method of manufacturing, the method comprising:

forming a plurality of structures on a workpiece using an in-line process metrology tool having at least one input value in a processing step;

measuring a parameter characteristic of the plurality of structures;

forming an output signal using the measured characteristic parameter and the at least one input value as inputs to a partial least squares transistor model;

predicting a wafer electrical test (WET) resulting value based on the output signal;

detecting faulty processing in the processing step based on the predicted WET resulting value; and

correcting the faulty processing.

38. The method of claim 37, wherein forming the output signal comprises using the partial least squares transistor model to map the input values to a set of WET measurement output values.

39. The method of claim 38, wherein using the partial least squares transistor model to map the input values to the set of WET measurement output values comprises using the partial least squares transistor model to define at least a subset of the input values having a significant effect on at least a subset of the WET measurement output values.

40. The method of claim 37, wherein correcting the faulty processing comprises inverting the partial least squares transistor model to define a change in the processing step needed to bring subsequent predicted WET resulting values within a range of specification values.

41. The method of claim 40, wherein inverting the partial least squares transistor model to define the change in the processing step comprises defining a change in a critical dimension of a feature formed in the processing step needed to bring the subsequent predicted WET resulting values within the range of specification values.

42. The method of claim 41, wherein defining the change in the critical dimension of the feature formed in the processing step comprises defining the change in the critical dimension of at least one of a poly gate line width, a spacer width of an MOS transistor, a poly gate line thickness, a gate dielectric thickness, and a silicide layer thickness of an MOS transistor.

43. The method of claim 40, wherein inverting the partial least squares transistor model to define the change in the processing step comprises defining a change in a doping level of a feature formed in the processing step needed to bring the subsequent predicted WET resulting values within the range of specification values.

44. The method of claim 43, wherein defining the change in the doping level of the feature formed in the processing step comprises defining the change in the doping level of a source/drain region of an MOS transistor or a source/drain extension (SDE) region of an MOS transistor.