System for calibrating timing of an integrated circuit wafer tester

• US 6,622,103 B1
• Filed: 06/20/2000
• Issued: 09/16/2003
• Est. Priority Date: 06/20/2000
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Primary Examiner(s): Nghiem, Michael
• Assistant Examiner(s): Lau, Tung S
• Application Number:
  US09/598,399
• Time in Patent Office: 1,183 Days
• Field of Search: 702/89, 702/119, 702/85, 324/158.1, 324/765
• US Class Current: 702/89
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/3191 Calibration

Abstract

A timing calibration system for a wafer level integrated circuit (IC) tester is disclosed. The tester includes channels linked by paths through an interconnect system to pads of the IC. During a test each channel may send a test signal edge to an IC pad following a clock signal edge with a delay including “programmable drive” delay and “drive calibration” delay components, or may sample an IC output signal following the clock signal edge with a delay including “programmable compare” delay and adjustable “compare calibration” delay components. The interconnect system also links a spare channel to a point on the IC. To adjust the compare calibration delay of each channel, the interconnect system sequentially connects the tester channels to interconnect areas on a “calibration” wafer instead of to the IC on the wafer to be tested. Each interconnect area provides a path linking a channel to be calibrated to the spare channel. With the programmable drive delay of the channel being calibrated and the programmable compare and compare calibration delays of the spare channel set to standard values, the drive calibration delay of the channel being calibrated is adjusted so it sends a test signal edge to the spare channel close to when the spare channel samples it. Pairs of tester channels are then interconnected through another wafer interconnect area. Each channel then sends a test signal edge to the other tester channel with a standard delay following a clock signal edge to provide a reference for calibrating the receiving channel'"'"'s compare calibration delay.

Claims

1. A method for calibrating timing of an integrated circuit (IC) tester and an interconnect system for connecting the IC tester to input/output (I/O) terminals of an IC implemented on a semiconductor wafer,

wherein the IC tester includes a plurality of tester channels for testing the IC implemented on the semiconductor wafer,

wherein the tester also includes a spare channel,

wherein the tester includes means for sending a sequence of clock signal edges to the tester channels and to the spare channel,

wherein the tester channels and the spare channel each include means for generating an output signal having an edge following receipt of any of said clock signal edges with a drive delay including a programmable drive delay and an adjustable drive calibration delay and for sampling an input signal following any of said clock signal edges with a compare delay including a programmable compare delay and an adjustable compare calibration delay, and

wherein the interconnect system contacts said IC to provide a first conductive path between each said I/O terminal and a corresponding one of said tester channels for conveying signals therebetween, the method comprising the steps of:

a. adapting said interconnect system to provide a second conductive path;

b. providing a plurality of first conductors, each corresponding to a separate one of said tester channels; and

c. for each tester channel of said plurality of tester channels;

c1. causing said interconnect system to contact the tester channel'"'"'s corresponding first conductor, wherein the corresponding first conductor and the first and second conductive paths form a first signal path between said tester channel and said spare channel,

c2. causing said tester channel to repeatedly send its output signal as an input signal to said spare channel via said first signal path, and

c3. concurrent with substep c2, causing said spare channel to sample its input signal with a fixed delay following said clock signal edges.

2. The method in accordance with claim 1 wherein step c further comprises the substeps of:

c4. concurrent with substeps c2 and c3, adjusting the calibration delay of the tester channel such that the tester channel sends said output signal to said spare channel with its output signal'"'"'s edge delayed from one of said clock signal edges such that the spare channel samples the output signal near said output signal edge.

3. The method in accordance with claim 2 further comprising the steps of:

d. providing a plurality of second conductors; and

e. following step c, causing said interconnect system to contact said second conductors, wherein the interconnect system and said second conductors provide second signal paths between pairs of the tester channels.

4. The method in accordance with claim 3 further comprising the steps of:

f. following step e, for each of said pairs;

f1. causing one tester channel of said pair to send an output signal having an output signal edge via said signal path to another tester channel of the pair, and

f2. concurrent with substep f1, adjusting the calibration delay of said another tester channel of the pair so that it samples the output signal near said output signal edge.

5. The method in accordance with claim 3 wherein said plurality of first conductors and said plurality of second conductors are implemented on said semiconductor wafer.

6. The method in accordance with claim 3 wherein said plurality of first conductors and said plurality of second conductors are implemented on a calibration wafer other than said semiconductor wafer.

7. The method in accordance with claim 1 wherein said plurality of said first conductors are implemented on said semiconductor wafer.

8. The method in accordance with claim 1 wherein said plurality of first conductors are implemented on a calibration wafer other than said semiconductor wafer.

9. A method for calibrating timing of an integrated circuit (IC) tester and an interconnect system,

wherein the IC tester has a plurality of tester channels for testing an IC implemented on a semiconductor wafer,

wherein the wafer has a plurality of input/output (I/O) terminals, each I/O terminal corresponding to a separate one of said tester channels,

wherein the tester includes means for sending a sequence of clock signal edges to the tester channels and to the spare channel,

wherein the tester channels and the spare channel each include means for generating an output signal having an edge following receipt of any of said clock signal edges with a drive delay including a programmable drive delay and an adjustable drive calibration delay and for sampling an input signal following any of said clock signal edges with a compare delay including a programmable compare delay and an adjustable compare calibration delay, and

wherein the interconnect system contacts said IC to provide a first conductive path between each said I/O terminal and its corresponding tester channel for conveying signals therebetween,

the method comprising the steps of:

a. providing a measurement circuit for measuring a time interval between an edge of the clock signal and an edge of an output signal of any one of said tester channels,

b. adapting said interconnect system to provide a second conductive path;

c. providing a plurality of first conductors, each corresponding to each of said tester channels; and

d. for each tester channel of said plurality of tester channels;

d1. causing said interconnect system to contact the tester channel'"'"'s corresponding first conductor, wherein the corresponding first conductor and the first and second conductive paths from a first signal path between said tester channel and said measurement circuit,

d2. causing said tester channel to produce output signal edges following said clock signal edges, wherein the first signal path conveys said output signal edges as input signal edges to said measurement circuit, and

d3. causing said measurement unit to measure intervals between said clock signal edges and its input signal edges arriving by said first signal path.

10. The method in accordance with claim 9 wherein step d further comprises the substeps of:

d4. concurrent with substep d2 and d3, adjusting the calibration delay of the tester channel so that said measurement unit measures intervals of a particular duration.

11. The method in accordance with claim 10 further comprising the steps of:

e. providing a plurality of second conductors; and

f. following step d, causing said interconnect system to contact said second conductors, wherein the interconnect system and said second conductors provide second signal paths between pairs of the tester channels.

12. The method in accordance with claim 11 further comprising the steps of:

g. for each of said pairs;

g1. causing one tester channel of said pair to send an output signal having an output signal edge via said signal path to another tester channel of the pair, and

g2. concurrent with substep g1, adjusting the calibration delay of said another tester channel of the pair so that it samples the output signal close to said output signal edge.

13. The method in accordance with claim 11 wherein said plurality of first conductors and said plurality of second conductors are implemented on said semiconductor wafer.

14. The method in accordance with claim 11 wherein said plurality of first conductors and said plurality of second conductors are implemented on a calibration wafer other than said semiconductor wafer.

15. The method in accordance with claim 9 wherein said plurality of said first conductors are implemented on said semiconductor wafer.

16. The method in accordance with claim 9 wherein said plurality of first conductors are implemented on a calibration wafer other than said semiconductor wafer.