12C bus expansion apparatus and method therefor

• US 6,622,188 B1
• Filed: 09/30/1998
• Issued: 09/16/2003
• Est. Priority Date: 09/30/1998
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Tuten, Wally, Hartman, Steven Paul, Goodwin, Joel Gerard, Isensee, Scott Harlan
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/163,992
• Time in Patent Office: 1,812 Days
• Field of Search: 710/101, 710/129, 710/128, 710/105, 710/126, 709/250, 709/230, 709/253, 370/466, 370/912
• US Class Current: 710/105
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

An apparatus and method for expansion of an inter-IC (I²C) is provided. An expansion processor resides on a primary I²C bus. The expansion processor is coupled to a plurality of I²C sub-buses each of which may host a plurality of I²C devices. Data is transferred between the expansion processor and the plurality of I²C devices via the corresponding sub-bus according to an I²C protocol. Data transfer is in response to a request initiated by a bus master on the primary I²C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which the echos it to the target device. Likewise, a data stream bound from the target device to the bus master on the primary I²C bus is transmitted to the expansion processor which the echos it to the bus master.

Claims

1. An apparatus for inter-IC (I²C) bus expansion comprising:

an expansion processor operable for communicating on an I²C bus, said expansion processor being coupled to a plurality of I²C sub-buses, wherein each sub-bus of said plurality of I²C sub-buses is operable for transferring data between said expansion processor and a plurality of I²C compatible devices according to an I²C protocol in response to signals on said I²C bus, wherein each said sub-bus comprises a serial clock line (SCL) and a serial data line (SDA), wherein said expansion processor further includes a set of input terminals operable for receiving a data value corresponding to an I²C address of said expansion processor on said I²C bus.

2. The apparatus of claim 1 wherein said expansion processor is operable for addressing in response to said data value.

3. The apparatus of claim 1 wherein said set of input terminals comprises a set of bidirectional input/output (I/O) terminals, and wherein a subset of said set of input terminals is operable for being coupled to one of said plurality of I²C sub-buses when said I²C address is one of a set of predetermined I²C addresses.

4. A data processing system comprising:

a central processing unit (CPU) operable for communicating on an inter-IC (I²C) bus, said CPU being operable as an I²C bus master; and

an expansion processor coupled to said I²C bus, said expansion processor being coupled to a plurality of I²C sub-buses, wherein each sub-bus of said plurality of I²C sub-buses is operable for transferring data between said expansion processor and a plurality of I²C compatible devices according to an I²C protocol in response to signals on said I²C bus, wherein each said sub-bus comprises a serial clock line (SCL) and a serial data line (SDA), wherein said expansion processor further includes a set of input terminals operable for receiving a data value corresponding to an I²C address of said expansion processor on said I²C bus.

5. The data processing system of claim 4 wherein said expansion processor is operable for addressing in response to said data value.

6. The data processing system of claim 4 wherein said set of input terminals comprises a set of bidirectional input/output (I/O) terminals, and wherein a subset of said set of input terminals is operable for being coupled to one of said plurality of I²C sub-buses when said I²C address is one of a set of predetermined I²C addresses.

7. A method for inter-IC (I²C) bus expansion comprising the steps of:

snooping a primary I²C bus for a preselected address;

on receiving said preselected address, selecting for a read operation and a write operation on a sub-bus in response to a preselected data value in a portion of said preselected address; and

in response to a write signal in said portion further comprises the steps of;

receiving and storing a first data value, said first data value designating a sub-bus, in response to said preselected address;

receiving and storing a second data value, said second data value representing an expansion device address, in response to said preselected address; and

sending said second data value on a sub-bus designated by said first data value.

8. The method of claim 7 further comprising the steps of:

receiving a third data value; and

sending said third data value on said sub-bus.

9. The method of claim 8 further comprising the steps of:

receiving a fourth data value, said fourth data value being received on said sub-bus;

if said fourth data value signals an acknowledgment, repeating said steps of receiving and sending said third data value and said step of receiving said fourth data value; and

if said fourth data value signals a no acknowledgment, clearing said sub-bus and sending an error signal on said primary bus.

10. The method of claim 9 further comprising the steps of:

receiving a fifth data value, said fifth data value being received on said primary bus;

if said fifth data value signals a stop condition;

terminating said repeating step; and

issuing a stop signal on said sub-bus.

11. A method for inter-IC (I²C) bus expansion comprising the steps of:

snooping a primary I²C bus for a preselected address;

on receiving said preselected address, selecting for a read operation and a write operation on a sub-bus in response to a preselected data value in a portion of said preselected address; and

in response to a read signal in said portion further comprises the steps of;

accessing an expansion device at a current address on a current sub-bus;

reading a first data byte from said expansion device; and

sending said first data byte on said primary bus.

12. The method of claim 11 further comprising the steps of:

receiving a second data value, said second data value being received on said primary bus;

if said second data value signals an acknowledgment, repeating said steps of receiving and sending said first data value and said step of receiving said second data value; and

if said second data value signals a no acknowledgment, issuing a stop signal on said sub-bus.

13. A computer program product adaptable for storage on program storage media, the program product operable for inter-IC (I²C) bus expansion, said program product comprising:

snooping a primary I²C bus for a preselected address;

programming for, on receiving said preselected address, selecting for a read operation and a write operation on a sub-bus in response to a preselected data value in a portion of said preselected address; and

in response to a write signal in said portion the program product further comprises;

programming for receiving and storing a first data value, said first data value designating a sub-bus, in response to said preselected address;

programming for receiving and storing a second data value, said second data value representing an expansion device address, in response to said preselected address; and

programming for sending said second data value on a sub-bus designated by said first data value.

14. The computer program product of claim 13 further comprising:

programming for receiving a third data value; and

programming for sending said third data value on said sub-bus.

15. The computer program product of claim 14 further comprising:

programming for receiving a fourth data value, said fourth data value being received on said sub-bus;

programming for repeating said steps of receiving and sending said third data value and said step of receiving said fourth data value in response to said fourth data value signaling an acknowledgment; and

programming for clearing said sub-bus and sending an error signal on said primary bus in response to said fourth data value signaling a no acknowledgment.

16. The computer program product of claim 15 further comprising:

programming for receiving a fifth data value, said fifth data value being received on said primary bus; and

programming for terminating said repeating step and issuing a stop signal on said sub-bus, if said fifth data value signals a stop condition.

17. A computer program product adaptable for storage on program storage media, the program product operable for inter-IC (I²C) bus expansion, said program product comprising:

snooping a primary I²C bus for a preselected address;

programming for, on receiving said preselected address, selecting for a read operation and a write operation on a sub-bus in response to a preselected data value in a portion of said preselected address;

programming for accessing an expansion device at a current address on a current sub-bus, in response to a read signal in said portion;

programming for reading a first data byte from said expansion device; and

programming for sending said first data byte on said primary bus.

18. The computer program product of claim 17 further comprising:

programming for receiving a second data value, said second data value being received on said primary bus;

programming for repeating said steps of receiving and sending said first data value and said step of receiving said second data value, if said second data value signals an acknowledgment; and

programming for issuing a stop signal on said sub-bus, if said second data value signals a no acknowledgment.