Method and apparatus for synchronizing interrupts in a message passing queue oriented bus system
First Claim
1. Apparatus for synchronizing an interrupt and DMA data generated by the same device in a message-passing, queue-oriented bus system having a memory and a DMA mechanism that sends a series of data packets comprising portions of the DMA data, via the bus system, to the memory and receives an acknowledgement for each data packet sent, the apparatus comprising:
- an interrupt queue that responds to the interrupt by generating and holding interrupt information;
a snapshot mechanism that responds to the interrupt by storing in the memory an indication of all data packets sent before the interrupt was generated for which acknowledgements have not been received; and
an interrupt synchronization mechanism that monitors received acknowledgements and cooperates with the snapshot mechanism to release the interrupt information when acknowledgements have been received for all data packets sent before the interrupt was generated.
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Accused Products
Abstract
In a message-passing, queue-oriented bus system, a separate interrupt work queue assigned to each interrupt line for each PCI device sends interrupt information packets from the device to the host. To prevent an interrupt from being transmitted before another DMA data write has been completed, interrupt requests are held on the interrupt work queue until all outstanding data transfer requests have been acknowledged. A special data structure called an interrupt scoreboard is created for each interrupt work queue entry associated with a DMA write in order to track the DMA data transfer. When an interrupt is received, the interrupt scoreboard acquires a “snapshot” of the state of the pending data requests and tracks the pending DMA transfers. When acknowledgement messages have been received for all pending DMA transfer requests, then the interrupt data packet is transmitted so that the interrupt can be serviced.
96 Citations
20 Claims
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1. Apparatus for synchronizing an interrupt and DMA data generated by the same device in a message-passing, queue-oriented bus system having a memory and a DMA mechanism that sends a series of data packets comprising portions of the DMA data, via the bus system, to the memory and receives an acknowledgement for each data packet sent, the apparatus comprising:
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an interrupt queue that responds to the interrupt by generating and holding interrupt information;
a snapshot mechanism that responds to the interrupt by storing in the memory an indication of all data packets sent before the interrupt was generated for which acknowledgements have not been received; and
an interrupt synchronization mechanism that monitors received acknowledgements and cooperates with the snapshot mechanism to release the interrupt information when acknowledgements have been received for all data packets sent before the interrupt was generated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for synchronizing an interrupt and DMA data generated by the same device in a message-passing, queue-oriented bus system having a memory and a DMA mechanism that sends a series of data packets comprising portions of the DMA data, via the bus system, to the memory and receives an acknowledgement for each data packet sent, the method comprising:
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(a) generating and holding interrupt information in an interrupt queue in response to the interrupt;
(b) in response to the interrupt, storing in the memory an indication of all data packets sent before the interrupt was generated for which acknowledgements have not been received; and
(c) monitoring received acknowledgements and releasing the interrupt information when acknowledgements have been received for all data packets sent before the interrupt was generated. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A computer program product for synchronizing an interrupt and DMA data generated by the same device in a message-passing, queue-oriented bus system having a memory and a DMA mechanism that sends a series of data packets comprising portions of the DMA data, via the bus system, to the memory and receives an acknowledgement for each data packet sent, the computer program product comprising a computer usable medium having computer readable program code thereon, including:
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program code for generating and holding interrupt information in an interrupt queue in response to the interrupt;
program code operable in response to the interrupt for storing in the memory an indication of all data packets sent before the interrupt was generated for which acknowledgements have not been received; and
program code for monitoring received acknowledgements and releasing the interrupt information when acknowledgements have been received for all data packets sent before the interrupt was generated. - View Dependent Claims (18, 19)
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20. A computer data signal embodied in a carrier wave for synchronizing an interrupt and DMA data generated by the same device in a message-passing, queue-oriented bus system having a memory and a DMA mechanism that sends a series of data packets comprising portions of the DMA data, via the bus system, to the memory and receives an acknowledgement for each data packet sent, the computer data signal comprising:
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program code for generating and holding interrupt information in an interrupt queue in response to the interrupt;
program code operable in response to the interrupt for storing in the memory an indication of all data packets sent before the interrupt was generated for which acknowledgements have not been received; and
program code for monitoring received acknowledgements and releasing the interrupt information when acknowledgements have been received for all data packets sent before the interrupt was generated.
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Specification