Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture

• US 6,622,198 B2
• Filed: 03/22/2001
• Issued: 09/16/2003
• Est. Priority Date: 08/31/2000
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: United Memories Incorporated (ProMOS Technologies, Inc.), Sony Corporation (Sony Group Corp.)
• Inventors: Jones, Jr., Oscar Frederick
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/815,148
• Publication Number:
  US 20020138685A1
• Time in Patent Office: 908 Days
• Field of Search: 711/101, 711/155, 711/110, 711/217, 711/218, 711/219, 711/167, 710/52, 710/39
• US Class Current: 711/101
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

A method for loading an integrated circuit FIFO at extremely high operating frequencies includes providing N logical locations, providing N+1 transparent latch stages, and providing N+1 write pointers, wherein two write pointers are contemporaneously enabled during a FIFO load operation. The method can be extended to enable three or more write pointers for even higher frequency operation.

Claims

1. A method for loading a FIFO comprising:

providing N logical locations;

providing N+1 latch stages; and

providing N+1 load pointer signals, wherein two load pointer signals are contemporaneously enabled during a FIFO load operations;

wherein a first latch stage receives an active first load pointer signal causing the first latch stage to transparently receive input data;

concurrently a second latch stage receives a second load pointer signal causing the second latch stage to transparently receive input data;

in response to a FIFO load command, the first load pointer signal goes inactive, latching data into the first latch stage, the second load pointer signal remains active, and a transparent path for input data to the second latch stage is maintained;

substantially simultaneously with loading the first latch stage, a third load pointer signal goes active causing a third latch stage to transparently receive input data; and

following the execution of the load command, the first latch stage contains latched data, while the load pointer signals for the second and third latch stages are active allowing a transparent path for input data to both the second and third latch stages.

2. The method of claim 1 further comprising:

storing data in an N−

1^th latch stage in response to a load command;

latching data into the N−

1^th latch stage by bringing the N−

1th load pointer inactive and retaining an Nth load pointer signal in the active state; and

substantially simultaneously with loading an N^th FIFO location, asserting an N+1^th load pointer signal to the active state resulting in load pointer signals for an N^th and N+1^th latch stages being active, allowing data to asynchronously pass to both the N^th and N+1^th latch stages as a precondition for a next FIFO load command.

3. The method of claim 2 wherein the FIFO load pointers wrap-around when a load pointer exceeds N+1.

4. The method of claim 1 wherein the method of loading a FIFO comprises loading a FIFO integrated circuit.

5. A method for loading a FIFO comprising:

providing N logical locations physically composed of N+2 latch stages;

providing N+2 load pointer signals wherein three load pointer signals;

wherein a first latch stage receives an active first load pointer signal causing the first latch stage to transparently receive input data;

concurrently second and third latch stages receive second and third active load pointer signals, respectively, causing the second and third latch stages to transparently receive input data;

in response to a FIFO load command, the first load pointer signal goes inactive, latching data into the first latch stage, the second and third load pointer signals remain active, maintaining a transparent oath for input data to the second and third latch stages; and

substantially simultaneously with loading the first latch stage, a fourth load pointer signal goes active making the fourth stage transparent to input data, and, following the execution of the load command, the first latch stage contains latched data, while the load pointer signals for the second, third, and fourth latch stages are active allowing a transparent oath for input data to the second, third, and fourth latch stages.

6. The method of claim 5 further comprising:

storing data in an N−

1^th latch stage in response to a load command;

latching data into the N−

1^th latch stage by bringing an N−

1^th load pointer signal inactive, retaining N^th and N+1^th load pointer signals in the active state; and

substantially simultaneously with loading an N^th FIFO location, asserting an N+2^th load pointer signal to the active state resulting in load pointer signals for N^th, N+1^th, and N+2^th latch stages being active allowing data input to asynchronously pass to the N^th, N+1^th, and N+2^th latch stages as a precondition for a next FIFO load command.

7. The method of claim 6 further comprising a wrap-around mode.

8. The method of claim 7 wherein the method of loading a FIFO comprises loading a FIFO integrated circuit.