System and method for maintaining memory coherency in a computer system having multiple system buses

• US 6,622,214 B1
• Filed: 01/12/1999
• Issued: 09/16/2003
• Est. Priority Date: 09/16/1996
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vogt, Pete D., White, George P., Chang, Stephen S.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Tran, Denise
• Application Number:
  US09/228,665
• Time in Patent Office: 1,708 Days
• Field of Search: 711/141, 711/143-145, 711/133, 711/159, 711/146, 711/124, 711/154, 711/130, 711/210, 710/100, 710/107, 710/128, 710/54-55, 710/305, 710/309-310
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)

Abstract

A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.

Claims

1. A coherency filter comprising:

a cycle encoder coupled to a set of tag controllers and to a rules table, the cycle encoder to determine a bus transaction type;

a tag memory array coupled to the cycle encoder, the tag memory array to record a coherency status of data values existing in a plurality of processors coupled to multiple buses; and

an invalidation queue coupled to the cycle encoder and to the tag memory array, the invalidation queue to store entries which are expelled from the tag memory array;

wherein the cycle encoder monitors transactions on a first bus and selectively inhibits cross-bus transactions to a second bus based on transaction type and corresponding rules retrieved from the rules table.

2. The coherency filter of claim 1, wherein the set of tag controllers comprises a control logic for direct mapping a cache line address into the tag memory array.

3. The coherency filter of claim 1, wherein the coherency status is maintained according to the MESI cache coherency protocol.

4. The coherency filter of claim 1, wherein the coherency status is maintained according to the MOESI cache coherency protocol.

5. The coherency filter of claim 1, wherein the rules table comprises:

a control logic to evaluate the bus transaction type information and remote coherency status bits obtained from the cycle encoder, the control logic further to perform snoop actions; and

a memory coupled to the control logic, the memory to store a truth table to maintain types of cross-bus transactions and local bus transactions to be executed to ensure cache coherency.

6. A method comprising:

monitoring transactions on a first bus which access a cache line in a main memory;

storing an address corresponding to the cache line;

determining a bus transaction type;

recording a coherency status of the cache line;

determining whether a cross-bus transaction to a second bus is necessary, based at least in part on a type of bus transaction and coherency status data;

expelling a cache line address when the cross-bus transaction is necessary; and

storing an expelled cache line.

7. The method of claim 6, wherein the coherency status comprises a status of the cache line in a cache memory of at least one processor.

8. The method of claim 6, wherein the coherency status is maintained according to the MESI cache coherency protocol.

9. The method of claim 6, wherein the coherency status is maintained according to the MOESI cache coherency protocol.