Digital clock skew detection and phase alignment

• US 6,622,255 B1
• Filed: 09/13/2000
• Issued: 09/16/2003
• Est. Priority Date: 09/13/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Barkatullah, Javed, Kurd, Nasser A.
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/660,808
• Time in Patent Office: 1,098 Days
• Field of Search: 713/400, 713/401, 713/500, 713/503
• US Class Current: 713/503
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03D 13/003 in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/15013 with more than two outputs
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence

Abstract

A skew measure circuit, an exclusion circuit, and an up/down counter are connected to form a skew detection circuit. The skew measure circuit asserts a first output signal if a first input clock leads a second input clock, and asserts a second output signal if the second clock leads the first clock. The exclusion circuit provides first and second digital pulse signals that represent the outputs of the skew measure circuit. The exclusion circuit also prevents the states of these pulse signals from changing, so long as the skew measure circuit is experiencing metastability. The up/down counter'"'"'s count is incremented in response to the first pulse signal and decremented in response to the other pulse signal.

Claims

1. An article of manufacture comprising:

a skew measure circuit to assert (1) a first output signal if a first digital input clock signal leads a second digital input clock signal, and (2) a second output signal if the second digital input clock signal leads the first digital input clock signal;

an exclusion circuit coupled to the skew measure circuit, to (1) provide first and second digital pulse signals that are representative of the first and second output signals and (2) prevent the states of the first and second digital pulse signals from changing so long as the skew measure circuit is experiencing metastability; and

a first up/down counter to provide a first count that is (1) incremented in response to the first digital pulse signal, and (2) decremented in response to the second digital pulse signal.

2. The article of manufacture of claim 1 further comprising:

a divider circuit to generate an enable signal that is coupled to qualify the first and second digital input clock signals, in response to one of the first and second digital input clock signals.

3. The article of manufacture of claim 2 wherein the divider circuit is to generate a reset signal that is coupled to reset the skew measure circuit, in response to one of the first and second digital input clock signals, prior to the skew measure circuit asserting one of the first and second output signals.

4. The article of manufacture of claim 1 further comprising:

a second up/down counter to provide a second count that is (1) decremented in response to the first digital pulse signal, and (2) incremented in response to the second digital pulse signal.

5. The article of manufacture of claim 4 further comprising:

a clock distribution network to provide the first and second digital input clock signals by first and second programmable delay circuits that are in respective branches of the network, the first and second delay circuits having respective control inputs to receive the first and second counts.

6. The article of manufacture of claim 4 further comprising:

a programmable delay circuit to provide (1) the first digital input clock signal by delaying a reference clock signal in accordance with the first count, and (2) the second digital input clock signal by delaying a feedback clock signal in accordance with the second count, the feedback clock signal being to be derived from a frequency control circuit.

7. The article of manufacture of claim 6 further comprising the frequency control circuit being coupled to enable the programmable delay circuit when it is phase locked.

8. The article of manufacture of claim 4 further comprising:

a programmable delay circuit to provide (1) the first digital input clock signal by delaying a first feedback clock signal in accordance with the first count, (2) the second digital input clock signal by delaying a second feedback clock signal in accordance with the second count, the first and second feedback clock signals to be derived from the outputs of first and second frequency control circuits that supply clocks to different clock domains.

9. The article of manufacture of claim 8 further comprising the first and second frequency control circuits being coupled to enable the programmable delay of the first and second feedback clock signals, respectively, when the first and second frequency control circuits are, respectively, phase locked.

10. The article of manufacture of claim 8 wherein each of the first and second frequency control circuits is to receive the same reference clock to which their outputs are phase locked.

11. The article of manufacture of claim 1 wherein the first count increments by one in response to each low to high transition in the first digital pulse, until reaching a maximum count.

12. The article of manufacture of claim 1 wherein the first count increments by a plurality of clock cycles while the first digital pulse is asserted.

13. An article of manufacture comprising:

means for detecting whether a first digital input clock signal leads or lags a second digital input clock signal;

means for providing first and second digital pulse signals that are representative of detecting that the first clock leads the second clock and that the second clock leads the first clock, respectively, the first and second digital pulse signals having fixed states while the detection means is experiencing metastability; and

means for providing a binary variable which changes in opposite directions in response to the first and second digital pulse signals.

14. The article of manufacture of claim 13 further comprising:

means for dividing one of the first and second digital input clock signals and then qualifying the first and second digital input clock signals, prior to detecting whether the first clock leads or lags the second clock using the qualified first and second clocks.

15. The article of manufacture of claim 14 further comprising:

means for resetting the detection means in response to one of the first and second digital input clock signals, prior to detecting whether the first clock leads or lags the second clock using the qualified first and second clocks.

16. A method comprising:

detecting whether a first digital input clock signal leads or lags a second digital input clock signal;

providing first and second digital pulse signals that are representative of detecting that the first clock leads the second clock and that the second clock leads the first clock, respectively, the first and second digital pulse signals having fixed states while the detection means is experiencing metastability; and

providing a binary variable which changes in opposite directions in response to the first and second digital pulse signals.

17. The method of claim 16 further comprising:

dividing one of the first and second digital input clock signals to qualify the first and second digital input clock signals prior to detecting whether the first clock leads or lags the second clock using the qualified first and second clocks.

18. The method of claim 17 further comprising:

resetting the first and second digital pulse signals in response to one of the first and second digital input clock signals, prior to detecting whether the first clock leads or lags the second clock using the qualified first and second clocks.