Semiconductor device and method of manufacturing thereof

• US 6,624,012 B2
• Filed: 04/12/2002
• Issued: 09/23/2003
• Est. Priority Date: 09/27/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Shibata, Hiroshi
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): CIESLEWICZ, ANETA B
• Application Number:
  US10/120,384
• Publication Number:
  US 20020132399A1
• Time in Patent Office: 529 Days
• Field of Search: 438/149, 438/151, 438/155, 438/164
• US Class Current: 438/155
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

To provide a liquid crystal display device having high quality display with a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a layer that is different from a gate electrode so that the capacitor wiring is arranged in parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of adjacent pixels can be avoided, thereby obtaining satisfactory display images.

Claims

1. A method of manufacturing a semiconductor device,

comprising the steps of:

forming an island shape semiconductor film over a substrate;

forming a first insulating film on the island shape semiconductor film;

forming an island shape gate electrode and a capacitor wiring;

forming a second insulating film covering the gate electrode and the capacitor wiring;

forming a first contact hole to reach the gate electrode by selectively etching the second insulating film;

forming a scanning line to be connected to the gate electrode on the second insulating film;

forming a third insulating film on the scanning line;

forming a second contact hole to reach the semiconductor film by selectively etching the third insulating film; and

forming a signal line to be electrically connected to the semiconductor film.

2. The method according to claim 1 wherein, after forming the first insulating film on the semiconductor film, the second insulating film which is overlapped with the scanning line is partly thinned.

3. The method according to claim 1 wherein said first insulating film is a gate insulating film.

4. A method of manufacturing a semiconductor device, comprising:

forming at least one semiconductor island;

forming a first insulating film on the semiconductor island;

forming a first conductive film on the first insulating film;

patterning the first conductive film into a gate electrode, wherein said gate electrode is shaped in an island;

introducing an impurity into selected regions of the semiconductor island to form at least source and drain regions therein wherein a channel region is formed between the source and drain regions;

forming a second insulating film over the gate electrode;

forming a first contact hole in the second insulating film to reach the gate electrode;

forming a second conductive film on the second insulating film; and

patterning the second conductive film to form a scanning line wherein the scanning line is electrically connected to the gate electrode through the first contact hole;

forming a third insulating film on the scanning line;

forming a third insulating film on the third insulating film; and

patterning the third insulating film to form a signal line wherein the signal line is electrically connected to the semiconductor island, wherein the signal line is isolated from the scanning line by at least said third insulating film interposed therebetween.

5. The method according to claim 4 wherein said first conductive film comprises a material selected from the group consisting of doped polysilicon, WSi_x (x=2.0 to 2.8), Al, Ta, W, Cr and Mo.

6. The method according to claim 4 wherein said second conductive film comprises a material selected from the group consisting of tungsten silicide, W, Cr and Al.

7. A method of manufacturing a semiconductor device, comprising:

forming at least one semiconductor island;

forming a first insulating film on the semiconductor island;

forming a first conductive film on the first insulating film;

patterning the first conductive film into a gate electrode and a capacitor wiring, wherein said gate electrode is shaped in an island;

forming a second insulating film over the gate electrode and the capacitor wiring;

forming a first contact hole in the second insulating film to reach the gate electrode;

forming a second conductive film on the second insulating film; and

patterning the second conductive film to form a scanning line wherein the scanning line is electrically connected to the gate electrode through the first contact hole;

forming a third insulating film on the scanning line;

forming a third conductive film on the third insulating film;

patterning the third conductive film to form a signal line wherein the signal line is electrically connected to the semiconductor island, wherein the signal line extends in an orthogonal direction to the scanning line and is isolated therefrom by at least said third insulating film interposed therebetween.

8. The method according to claim 7 wherein said first conductive film comprises a material selected from the group consisting of doped polysilicon, WSi_x (x=2.0 to 2.8), Al, Ta, W, Cr and Mo.

9. The method according to claim 7 wherein said second conductive film comprises a material selected from the group consisting of tungsten silicide, W, Cr and Al.

10. A method of manufacturing a semiconductor device, comprising:

forming at least one semiconductor island;

forming a first insulating film on the semiconductor island;

forming a first conductive film on the first insulating film;

patterning the first conductive film into a gate electrode and a capacitor wiring, wherein said gate electrode is shaped in an island;

forming a second insulating film over the gate electrode and the capacitor wiring;

forming a first contact hole in the second insulating film to reach the gate electrode;

forming a second conductive film on the second insulating film; and

patterning the second conductive film to form a scanning line wherein the scanning line is electrically connected to the gate electrode through the first contact hole;

forming a third insulating film on the scanning line;

forming a third insulating film on the third insulating film;

patterning the third insulating film to form a signal line wherein the signal line is electrically connected to the semiconductor island through the second contact hole, wherein the signal line extends in parallel with said capacitor wiring.

11. The method according to claim 10 wherein said first conductive film comprises a material selected from the group consisting of doped polysilicon, WSi_x (x=2.0 to 2.8), Al, Ta, W, Cr and Mo.

12. The method according to claim 10 wherein said second conductive film comprises a material selected from the group consisting of tungsten silicide, W, Cr and Al.

13. A method of manufacturing a semiconductor device, comprising:

forming at least one semiconductor island;

forming a first insulating film on the semiconductor island;

forming a first conductive film on the first insulating film;

patterning the first conductive film into a gate electrode and a capacitor wiring, wherein said gate electrode is shaped in an island;

forming a second insulating film over the gate electrode and the capacitor wiring;

forming a first contact hole in the second insulating film to reach the gate electrode;

forming a scanning line on the second insulating film wherein the scanning line is electrically connected to the gate electrode through the first contact hole and extends in an orthogonal direction to the capacitor wiring;

forming a third insulating film on the scanning line;

forming a signal line on the third insulating film wherein the signal line is electrically connected to the semiconductor island, wherein the signal line extends in parallel with and overlaps said capacitor wiring.

14. The method according to claim 13 wherein said first conductive film comprises a material selected from the group consisting of doped polysilicon, WSi_x (x=2.0 to 2.8), Al, Ta, W, Cr and Mo.

15. The method according to claim 13 wherein said second conductive film comprises a material selected from the group consisting of tungsten silicide, W, Cr and Al.