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Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions

  • US 6,624,015 B2
  • Filed: 11/09/2001
  • Issued: 09/23/2003
  • Est. Priority Date: 07/22/1998
  • Status: Expired due to Term
First Claim
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1. A method for manufacturing electronic devices, memory cells and low voltage (LV) transistors with salicided junctions, comprising:

  • depositing an upper layer of polycrystalline silicon;

    defining the said upper layer to obtain LV gate regions and undefined portions;

    forming LV source and drain regions laterally to said LV gate regions;

    forming a silicide layer on said LV source and drain regions, on said LV gate regions, and on said undefined portions; and

    defining cell gate regions.

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