Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions

• US 6,624,015 B2
• Filed: 11/09/2001
• Issued: 09/23/2003
• Est. Priority Date: 07/22/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Patelmo, Matteo, Vajana, Bruno, Galbiati, Nadia, Dalla Libera, Giovanna
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US10/010,049
• Publication Number:
  US 20020040993A1
• Time in Patent Office: 683 Days
• Field of Search: 438/201, 438/211, 438/258, 438/266, 438/275, 438/592, 438/593, 438/594
• US Class Current: 438/201
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Claims

1. A method for manufacturing electronic devices, memory cells and low voltage (LV) transistors with salicided junctions, comprising:

depositing an upper layer of polycrystalline silicon;

defining the said upper layer to obtain LV gate regions and undefined portions;

forming LV source and drain regions laterally to said LV gate regions;

forming a silicide layer on said LV source and drain regions, on said LV gate regions, and on said undefined portions; and

defining cell gate regions.

2. The method of claim 1, further comprising forming HV transistors, and wherein defining cell gate regions further comprises defining HV gate regions.

3. The method of claim 2, further comprising, before depositing an upper layer:

forming first gate oxide regions on first areas of a substrate of monocrystalline silicon;

forming polycrystalline silicon regions on said first gate oxide regions;

forming dielectric regions on said polycrystalline silicon regions;

forming second gate oxide regions on second areas of said substrate, and third gate oxide regions on third areas of said substrate;

wherein said LV gate regions extend on said second areas and said undefined portions extend on said first and said third areas;

and wherein defining gate regions of cells comprises;

removing selective portions of said silicide layer and of said upper layer from above said first and third areas, such as to form said HV gate regions on said third areas, as well as upper gate structures on said first areas;

removing selective portions of said dielectric layer and of said polycrystalline silicon regions from above said first areas, in an aligned manner with said upper gate structures;

the method then further comprising forming HV source and drain regions in said third areas adjacent to said HV gate regions, and cell source and drain regions in said first areas adjacent to said upper gate structures.

4. The method of claim 3, wherein said memory cells are EEPROM cells comprising a selection transistor and a memory transistor,

wherein forming first gate oxide regions further comprises forming continuity regions in said first areas, and providing tunnel oxide regions on said continuity regions;

wherein forming dielectric regions further comprises removing selective portions of said dielectric regions such that, during depositing an upper layer, areas of contact are formed between said polycrystalline regions and said upper layer;

and simultaneously with forming LV source and drain regions, forming a source region of said memory transistor;

and wherein removing selective portions of said silicide layer further comprises defining two sides of upper gate portions of said selection transistor, and one side of control gate regions of said memory transistor;

and wherein removing selective portions of said dielectric layer is carried out in an aligned manner with said two sides of said upper gate portions of said selection transistor and with said side of said control gate regions such as to form lower gate portions of said selection transistors, shorted to said upper gate portions and floating gate regions of said memory transistor;

and wherein forming HV and cell source drain regions further comprises the step of forming source and drain regions of said selection transistor.

5. The method of claim 4, further comprising forming said source region of said memory transistor, said source and drain regions of said selection transistor, and said LV and HV source and drain regions to have a first conductivity type, and further comprising, before forming first gate oxide regions:

first selective implanting of doping ionic species of a second conductivity type in said first and third areas of said substrate;

second implanting, separate from the first implanting, of doping ionic species of said second conductivity type in said second areas of said substrate which do not cover said first and third areas.

6. The method of claim 4, wherein forming polycrystalline silicon regions comprises:

depositing a lower layer of polycrystalline silicon;

removing said lower layer completely from above said second and third areas, and removing selective portions of said lower layer from above said first areas, such as to form a first, a second and a third side of a quadrilateral, said first and second sides being opposite to one another, and said third side extending between said first and second sides of said quadrilateral; and

forming lightly doped drain (LDD) cell regions in said first areas, laterally to said third side of said quadrilateral, said LDD cell regions being spaced from said regions of continuity;

and further comprising forming said dielectric regions to cover said first, second and third sides of said quadrilateral.

7. The method of claim 4, further comprising, simultaneously with removing selective portions of said dielectric regions, removing selective portions of said dielectric layer from above said first areas, and laterally to said polycrystalline silicon regions, and after defining said upper layer, and before forming LV source and drain regions, further comprising:

implanting doping ionic species in said LV gate regions, in said undefined portions, and in said first and third areas, and forming LV LDD regions aligned with said LV gate regions in said second areas, and intermediate cell source regions in said first areas, aligned with said dielectric layer, said intermediate cell source regions being intended to laterally surround said source regions of said memory transistor; and

forming first and second spacers laterally to said LV gate regions, respectively laterally to said dielectric layer on said first areas;

and wherein forming LV source and drain regions and source regions of said memory transistor are carried out aligned with said first and second spacers.

8. A method for manufacturing electronic devices having memory cells and transistors with salicided junctions, comprising:

forming active area array regions of a first conductivity and active area regions of low voltage (LV) conductivity in a substrate;

defining LV gate regions on the active area regions of LV conductivity;

forming LV source and drain regions laterally to the LV gate regions in the active area regions of LV conductivity;

forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the active area array regions; and

defining memory cell gate regions in the active area array regions.

9. The method of claim 8, wherein forming active area array regions further comprises forming an area active region of high voltage (HV) conductivity, and defining cell gate regions further comprises defining HV gate regions.

10. A method for manufacturing electronic devices having memory cells and low voltage (LV) and high voltage (HV) transistors, comprising:

forming an active region of LV conductivity in a first area in a silicon substrate, and an active HV region and an active array region of a second conductivity in second and third areas in the substrate of silicon, respectively;

forming a first gate oxide region on the third area;

forming a polycrystaline silicon region on the first gate oxide region;

forming a dielectric region on the polycrystaline silicon region;

forming a second gate oxide region on the second area of the substrate and a third gate oxide region on the first area of the substrate;

depositing an upper layer of polycrystaline silicon over selected regions of the first, second, and third areas;

defining an LV gate region in the third area;

forming LV source and drain regions laterally to the LV gate region;

forming a silicide layer on the LV source and drain region, on the LV gate region, and on the upper layer of polycrystaline silicon on the first and second regions; and

defining HV gate regions in the second region and cell gate regions in the third region.

11. The method of claim 10, wherein defining the cell gate regions comprises:

removing selected portions of the silicide layer and the upper layer of polycrystaline silicon from above the second and first areas to form the high voltage (HV) gate region on the second area and upper gate structures on the first area; and

removing selected portions of the dielectric layer and the polycrystaline silicon regions from above the third area in an aligned manner with the upper gate structures.

12. The method of claim 11, further comprising forming HV source and drain regions in the second area adjacent to the HV gate regions and cell source and drain regions in the third area adjacent to the upper gate structures.