Method for forming gate segments for an integrated circuit

• US 6,624,021 B2
• Filed: 07/24/2001
• Issued: 09/23/2003
• Est. Priority Date: 04/25/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, LONG K
• Application Number:
  US09/911,688
• Publication Number:
  US 20010055221A1
• Time in Patent Office: 791 Days
• Field of Search: 365/149, 257/522, 257/301, 438/257, 438/253, 438/254, 438/238, 438/239, 438/381, 438/396-399
• US Class Current: 438/253
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A method for forming gate segments in an integrated circuit. The method begins by forming a shallow trench isolation region outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit. After the isolation region is formed, at least one gate segment is formed in each active region by depositing, planarizing and selectively etching a conductive material. Source/drain regions are also formed in the active region. The active regions are selectively interconnected with edge-defined conductors that pass outwardly from the gate segments and the shallow trench isolation region to form the integrated circuit.

Claims

1. A method for forming an electronic system having a gate for an integrated circuit component, comprising:

isolating an active region of a layer of semiconductor material;

disposing a thin insulating layer outwardly from the active region;

depositing a layer of conductive material outwardly from the insulating layer after isolating the active region;

selectively removing portions of the conductive material, and the insulating layer to form the gate.

2. The method of claim 1, wherein isolating the active region includes forming a shallow trench isolation region around the active region.

3. The method of claim 1, further including doping the exposed semiconductor material after the selective removal to form source/drain regions.

4. The method of claim 1, wherein depositing a conductive layer includes depositing a layer of poly-silicon material.

5. The method of claim 1, wherein selectively removing portions of the conductive material and the insulating layer forms two gate segments.

6. A method for forming an electronic system having a gate for an integrated circuit component comprising:

isolating an active region of a layer of semiconductor material;

disposing a first insulative layer outwardly from the active region;

depositing a layer of first conductive material outwardly from the first insulative layer after isolating the active region;

selectively removing portions of the first conductive material and the first insulative layer to form the gate;

capping the gate with a pad layer;

forming contacts for a source region and a drain region;

forming a second insulative layer on the contacts for the source and drain regions;

forming a mandrel on the second insulative layer and the pad layer;

selectively etching the mandrel to remove at least a portion of the pad layer to expose the gate; and

forming a second conductive material on at least a portion of the exposed gate.

7. The method of claim 6, wherein isolating the active region includes forming a shallow trench isolation region around the active region.

8. The method of claim 6, wherein capping the gate with a pad layer includes capping the gate with a nitride pad layer.

9. The method of claim 6, wherein forming contacts for a source region and a drain region includes:

forming insulating sidewalls adjacent the gate; and

depositing a third conductive material adjacent to and contacting the insulating sidewalls opposite the gate.

10. The method of claim 6, wherein the method further includes anisotropically etching the second conductive material to form a sub-lithographic contact to the gate.

11. The method of claim 6, wherein selectively removing portions of the first conductive material and the first insulative layer forms two gate segments.

12. A method for forming an electronic system having a gate for an integrated circuit component, comprising:

isolating an active region of a layer of semiconductor material;

disposing a thin insulating layer outwardly from the active region;

depositing a layer of first conductive material outwardly from the insulating layer after isolating the active region;

selectively removing portions of the first conductive material and the insulating layer to form the gate;

capping the gate with a pad layer;

selectively etching at least a potion of the pad layer to expose the gate;

forming a second conductive material on at least a portion of the exposed gate; and

anisotropically etching the second conductive material to form a sub-lithographic contact to the gate.

13. The method of claim 12, wherein isolating the active region includes forming a shallow trench isolation region around active region.

14. The method of claim 12, further including doping the semiconductor material to form source/drain regions after selectively removing portions of the first conductive material and the insulating layer to form the gate.

15. The method of claim 12, wherein depositing a layer of first conductive material outwardly from the insulating layer after isolating the active region includes depositing a layer of poly-silicon material.

16. The method of claim 12, wherein selectively removing portions of the first conductive material and the insulating layer forms two gate segments.

17. A method for forming an electronic system having a gate for an integrated circuit component, comprising:

isolating an active region of a layer of semiconductor material;

disposing a first insulative layer outwardly from the active region;

depositing a layer of first conductive material outwardly from the first insulative layer after isolating the active region;

selectively removing portions of the first conductive material and the insulating first insulative layer to form the gate;

capping the gate with pad layer;

forming contacts for two source/drain regions;

forming a second insulative layer on the contacts for the two source/drain regions;

forming a mandrel on the second insulative layer and the pad layer;

selectively etching the mandrel to remove at least a portion of the pad layer to expose the gate; and

forming a second conductive material on at least a portion of the exposed gate;

anisotropically etching the second conductive material to form a gate contact;

forming a plate of a capacitor coupled to one contact for the two source/drain regions; and

coupling the contact for the second of the two source/drain regions to a metal conductive line.

18. The method of claim 17, wherein isolating the active region includes forming a shallow trench isolation region around the active region.

19. The method of claim 17, wherein the method further includes forming the plate of the capacitor while forming final region of conductive material coupling the metal conductive line to the contact for the second of the two source/drain regions.

20. The method of claim 17, wherein selectively removing portions of the first conductive material and the first insulative layer forms two gate segments.

21. A method for forming an electronic system having a gate for an integrated circuit component, comprising:

isolating an active region of a layer of semiconductor material;

disposing a first insulating layer outwardly from the active region;

depositing a layer of first conductive material outwardly from the first insulative layer after isolating the active region;

selectively removing portions of the first conductive material and the insulating first insulative layer to form the gate;

capping the gate with a pad layer;

forming two source/drain regions;

forming insulating sidewalls adjacent to and extending above the gate;

depositing a second conductive material adjacent to and contacting the insulating sidewalk opposite the gate, the second conductive material forming contacts to the two source/drain regions;

forming a third conductive material on at least a portion of the exposed gate.

anisotropically etching the third conductive material to form a gate contact, the gate contact extending above the insulating sidewalls adjacent the gate;

forming a second insulating layer on the remaining portion of the exposed gate between the insulating sidewalk that extend above the gate;

capping an end of the gate contact to the gate opposite the gate;

forming a plate of a capacitor conductively coupled to one of the two source/drain regions, the plate formed at a level above the capped end of the gate contact; and

coupling the contact to the second of the two source/drain regions to a metal conductive line.

22. The method of claim 21, wherein isolating the active region includes forming a shallow wench isolation region around the active region.

23. The method of claim 21, wherein the method further includes forming a second plate of the capacitor, the second plate including platinum.

24. The method of claim 21, wherein the method further includes forming silicon dioxide as the second insulating layer on the remaining portion of the exposed gate between the insulating sidewalls that extend above the gate.

25. The method of claim 21, wherein selectively removing portions of the first conductive material and the first insulative layer forms two gate segments.

26. A method for forming an electronic system having a gate for an integrated circuit component, comprising:

isolating an active region of a layer of semiconductor material;

disposing a first insulating layer outwardly from the active region;

depositing a layer of first conductive material outwardly from the first insulating layer after isolating the active region;

selectively removing portions of the first conductive material and the first insulating layer to form the gate, wherein selectively removing portions of the first conductive material and the first insulating layer form two gate segments;

forming three source/drain regions, one source/drain region formed as a common drain for two transistors, one of the two transistors using one of the two gate segments and the other transistor using the other of the two gate segments;

forming two capacitors, one capacitor coupled to one of the two transistor and the other capacitor coupled to the second transistor; and

forming a contact to the source/drain region formed as the common drain to couple the common drain to a metal conductive line.

27. The method of claim 26, wherein the method further includes forming a sub-lithographic contact to each of the two gate segments.

28. The method of claim 26, wherein the method further includes forming a separate gate contact to each of the two gate segments and forming the two capacitors as stacked capacitors at a level above the gate contacts.

29. The method of claim 26, wherein forming two capacitors includes forming each capacitor with a first conductive plate using poly-silicon and a second conductive plate using a metallic conductor.

30. The method of claim 26, wherein the method further includes forming a lower plate of each capacitor while forming a final region of conductive material coupling the contact to the source/drain region formed as the common drain to the metal conductive line.

31. A method for forming an electronic system having a gate for an integrated circuit component, comprising:

isolating an active region of a layer of semiconductor material;

disposing a first insulating layer outwardly from the active region;

depositing a layer of first conductive material outwardly from the first insulating layer after isolating the active region;

selectively removing portions of the first conductive material and the first insulating layer to form the gate, wherein selectively removing portions of the first conductive material and the first insulating layer forms two gate segments;

forming a second conductive material on at least a portion of the two gate segments;

anisotropically etching the second conductive material to form a gate contact to each of the two gate segments;

forming three source/drain regions, one source/drain region formed as a common drain for two transistors, one of the two transistors using one of the two gate segments and the other transistor using the second other of the two gate segments;

forming a contact to the source/drain region formed as the common drain, the contact coupled to a conductive metal line; and

coupling each gate contact to separate conductive lines.

32. The method of claim 31, wherein isolating the active region includes forming a shallow trench isolation region around the active region.

33. The method of claim 31, wherein the method further includes forming a bit line as the conductive metal line coupled to the source/drain region formed as the common drain.

34. The method of claim 31, wherein anisotropically etching the second conductive material to form a gate contact to each of the two gate segments forms the gate contacts as sub-lithographic segments of word lines.

35. A method of forming a memory device having a gate for an integrated circuit component, comprising:

forming an array of removing cells interconnected with a plurality of bit lines and word lines, wherein forming each cell includes forming an activation device with gates formed as segments that are separated by, and are self-aligned with, a shallow trench isolation region; and

coupling an addressing circuit to the array of memory cells to allow selective access to the memory cells, wherein forming the gate segments for the activation device includes

isolating an active region of a layer of semiconductor material;

disposing a thin insulating layer outwardly from the active region;

depositing a layer of conductive material outwardly from the insulating layer after isolating the active region;

selectively removing portions of the conductive material and the insulating layer to form the gate.

36. The method of claim 35, wherein the method further includes doping the active region of the semiconductor material after the selective removal to form source/drain regions.

37. The method of claim 35, wherein forming an array of memory cells includes forming a plurality of cells in a folded bit line configuration.

38. The method of claim 35, wherein forming an array of memory includes forming stacked capacitors for storing data.

39. A method of forming a memory system having a gate for an integrated circuit component, comprising:

providing a processor;

coupling a memory device to the processor, the memory device formed by a method comprising;

forming an array of memory cells interconnected with a plurality of bit lines and word lines, the word lines including sub-lithographic word lines, forming each cell includes forming an activation device with gates formed as segments that are separated by and self-aligned with a shallow trench isolation region; and

coupling an addressing circuit to the array of memory cells to allow selective access to the memory cells, wherein forming the gate segments for the activation device includes

isolating an active region of a layer of semiconductor material;

disposing a thin insulating layer outwardly from the active region;

depositing a layer of conductive material outwardly from the insulating layer after isolating the active region;

selectively removing portions of the conductive material and the insulating layer to form the gate.

40. The method of claim 39, wherein the method further includes doping the active region of the semiconductor material after the selective removal to form source/drain regions.

41. The method of claim 39, wherein forming an array of memory cells includes forming a plurality of cells in a folded bit line configuration.

42. The method of claim 39, wherein forming an array of memory cells includes forming stacked capacitors for storing data.

43. A method of forming a memory system having a gate for an integrated circuit component, comprising:

providing a control circuit; and

coupling a memory device to the control circuit, wherein the memory device is formed by a method including;

isolating active regions of a layer of semiconductor material by forming a shallow trench isolation region with a pad that extends outwardly from the layer of a semiconductor material to form active regions;

disposing a thin insulating layer outwardly from the active regions;

disposing a conductive layer outwardly from the insulating layer after isolating the active region;

planarizing the conductive layer such that a working surface of the conductive layer is substantially coplanar with a surface of the shallow trench isolation region;

forming at least one gate segment in each active region, wherein the at least one gate segment is formed by selectively removing portions of the conductive layer and the insulating layer from the active regions;

forming a plurality of source/drain regions in the portions of the active regions not covered by the conductive layer;

selectively interconnecting a plurality of word lines with the gate segments; and

selectively coupling a plurality of bit lines and storage capacitors to the source/drain regions to form an array of cells for the memory device.

44. The method of claim 43, wherein providing a control circuit includes providing a microprocessor.

45. The method of claim 43, wherein forming the memory device includes forming a dynamic random access memory.

46. The method of claim 43, wherein disposing a conductive layer includes depositing a poly-silicon layer.

47. The method of claim 43, wherein selectively interconnecting a plurality of word lines with the gate segments includes forming the gate segments as a folded bit line array of memory cells.

48. The method of claim 43, wherein forming a shallow trench isolation region includes etching a trench into the layer of semiconductor material and filling the trench with an oxide layer, wherein the trench isolates a number of active regions.

49. The method of claim 43, wherein selectively interconnecting a plurality of word lines with the gate segments includes selectively interconnecting a plurality of edge-defined word lines with the gate segments.

50. The method of claim 43, wherein forming at least one gate segment in each active region includes forming two gate segments in each active region.

51. A method of forming a pair of memory cells of an electronic system having a gate for an integrated circuit, comprising:

forming two transistors in a semiconductor material, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor formed as segments that are separated by and self-aligned with a shallow trench isolation region, wherein the gate of each transistor extends outwardly from the semiconductor material, wherein forming each gate includes;

isolating an active region of a layer of semiconductor material;

disposing a thin insulating layer outwardly from the active region;

depositing a layer of conductive material outwardly from the insulating layer after isolating the active region; and

selectively removing portions of the conductive material and the insulating layer to form the gate.;

forming two word lines outwardly from the transistors, wherein the word lines include sub-lithographic word lines and each word line having a width less than a minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors;

forming a bit line and two conductors outwardly from the transistors, the bit line coupled to the shared drain of the transistors each conductor coupled to the source of a different transistor, the bit line and the two conductors adjacent to the word lines; and

forming two storage capacitors outwardly from the bit line and the conductors, each storage capacitor coupled to a source of a different transistor by one of the conductors.

52. The method of claim 51, wherein the method further includes doping the active region of the semiconductor material after the selective removal to form source/drain regions.

54. The method of claim 51, wherein the method further includes doping the exposed semiconductor material after the selective removal to form source/drain regions.

55. The method of claim 51, wherein interconnecting an array of memory cells includes interconnecting a plurality of cells formed in a folded bit line configuration.

56. The method of claim 51, wherein forming each cell includes forming a stacked capacitor for storing data.

53. A method of forming an electronic system having a gate for an integrated circuit component, comprising:

providing a microprocessor;

coupling a memory device to the microprocessor, wherein the memory device is formed by a method comprising;

coupling a column decoder with input output circuitry to a plurality of bit lines and to a plurality of bit complement lines;

coupling a row decoder to a plurality of word lines;

coupling at least one address buffer to the row decoder and column decoder, wherein the address buffer receives an address of a selected cell and identifies a word line of the selected cell to the row decoder;

coupling each sense amplifier of a plurality of sense amplifiers to a corresponding pair of bit line and bit complement line; and

interconnecting an array of memory cells with the plurality of bit lines and word lines, the word lines including sub-lithographic word lines, wherein forming each cell includes forming an activation, device with gates formed as segments that are separated by and self-aligned with a shallow trench isolation region, wherein forming the gate segments for the activation device includes

isolating an active region of a layer of semiconductor material;

disposing a thin insulating layer outwardly from the active region;

depositing a layer of conductive material outwardly from the insulating layer after isolating the active region;

selectively removing portions of the conductive material and the insulating layer to form the gate.