Semiconductor device having an insulated gate and a fabrication process thereof

• US 6,624,483 B2
• Filed: 03/28/2001
• Issued: 09/23/2003
• Est. Priority Date: 07/12/2000
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Kurata, Hajime
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/818,651
• Publication Number:
  US 20020005581A1
• Time in Patent Office: 909 Days
• Field of Search: 257/387, 257/412, 257/413, 257/755, 257/756, 257/347, 257/410, 257/411, 257/616
• US Class Current: 257/387
• CPC Class Codes: H01L 21/2807 the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A semiconductor device includes a T-shaped gate on a gate insulation film, wherein the T-shaped gate includes a lower polycrystal layer containing Si and Ge and an upper polycrystal layer of polysilicon.

Claims

1. A semiconductor device, comprising:

a substrate including a semiconductor layer at least on a top part thereof;

a gate insulation film provided on said semiconductor layer; and

a gate electrode provided on said gate insulation film, said gate electrode comprising a first polycrystal layer in contact with said gate insulation film, said first polycrystal layer containing at least Si and Ge, and a second polycrystal layer provided on said first polycrystal layer, said second polycrystal layer being a polysilicon layer,

wherein said first polycrystal layer has a reduced lateral size as compared with said second polycrystal layer, said first and second polycrystal layers thereby forming a T-shaped gate electrode, and

wherein said first polycrystal layer has an oxidation rate larger than an oxidation rate of said second polycrystal layer.

2. A semiconductor device as claimed in claim 1, wherein said first polycrystal layer further contains C.

3. A semiconductor device as claimed in claim 2, wherein said first polycrystal layer contains C with a concentration of about 1.5 at %.

4. A semiconductor device as claimed in claim 1, wherein said first polycrystal layer is doped with any of B, P and As.

5. A semiconductor device as claimed in claim 1, wherein said semiconductor device has a bulk silicon substrate.

6. A semiconductor device as claimed in claim 1, wherein said semiconductor device has a silicon-on-insulator substrate.