Three-dimensional, mask-programmed read only memory

• US 6,624,485 B2
• Filed: 11/05/2001
• Issued: 09/23/2003
• Est. Priority Date: 11/05/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Johnson, Mark G.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): SMITH, BRADLEY
• Application Number:
  US10/010,643
• Publication Number:
  US 20030086284A1
• Time in Patent Office: 687 Days
• Field of Search: 257/390, 257/529, 257/258, 257/259, 257/530, 365/103
• US Class Current: 257/390
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM

Abstract

A 3-dimensional read only memory includes vertically stacked layers of memory cells. Each of the memory cells includes a mask programmed insulating layer, a pair of diode components, and a pair of crossing-conductors. The conductors (other than those at the top and the bottom of the array) each connect to both overlying conductors via overlying memory cells and to underlying conductors via underlying memory cells.

Claims

1. A 3-dimensional read only memory array comprising:

a substrate;

a layer of first conductors overlying the substrate;

a first, mask-programmed, insulating layer overlying the layer of first conductors;

a layer of second conductors overlying the first insulating layer, said second conductors each positioned to cross over multiple ones of said first conductors;

a second, mask-programmed, insulating layer overlying the layer of second conductors; and

a layer of third conductors overlying the second insulating layer, said third conductors each positioned to cross over multiple ones of the second conductors;

a plurality of first memory cells, each extending across the first insulating layer and positioned at an intersection of a respective first conductor and a respective second conductor; and

a plurality of second memory cells, each extending across the second insulating layer and positioned at an intersection of a respective second conductor and a respective third conductor;

each of said memory cells comprising a respective first diode component and a respective second diode component.

2. The 3-dimensional read only memory array of claim 1 wherein said diode components provide each memory cell with a preferred current conduction direction, and wherein said diode components are arranged such that for each set of crossing first, second and third conductors, the preferred current directions of the first and second memory cells aligned with the respective conductors are oppositely directed with respect to one another.

3. The 3-dimensional read only memory array of claim 1 wherein the first and second insulating layers comprise a material selected from the group consisting of:

silicon dioxide, silicon nitride, ONO, amorphous silicon, tantalum pentoxide, PZT ferroelectric insulators, chalcogenide insulators, organic insulators, polyimide insulators, and combinations thereof.

4. The 3-dimensional read only memory array of claim 1 wherein the first and second diode components for at least first ones of the memory cells in a selected logic state form respective diodes selected from the group consisting of:

P-N diodes, Schottky diodes, polysilicon diodes, micro-crystalline silicon diodes, micro-crystalline semiconductor diodes, germanium diodes, silicon-germanium diodes, gallium-arsenide diodes.

5. The 3-dimensional read only memory array of claim 1 wherein, for at least some of the memory cells, the respective first and second diode components are disposed on opposite sides of the respective insulating layer.

6. The 3-dimensional read only memory array of claim 1 wherein, for at least some of the memory cells, the respective first and second diode components are disposed on a first side of the respective insulating layer.

7. The 3-dimensional read only memory array of claim 1 wherein each insulating layer comprises an array of insulating portions and an array of conducting portions, wherein some of the memory cells extend across respective conducting portions, and wherein some of the memory cells extend across respective insulating portions.

8. The 3-dimensional read only memory array of claim 7 wherein the conducting portions comprise openings in the insulating layers.

9. The 3-dimensional read only memory array of claim 1 wherein the first conductors are parallel to and spaced apart from one another, wherein the second conductors are parallel to and spaced apart from one another, and wherein the third conductors are parallel to and spaced apart from one another.

10. The 3-dimensional read only memory array of claim 9 wherein the first and third conductors are parallel to one another and orthogonal to the second conductors.