Semiconductor device and method for manufacturing the same

• US 6,624,504 B1
• Filed: 10/30/2000
• Issued: 09/23/2003
• Est. Priority Date: 10/29/1999
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Advanced Technologies Inc. (f/k/a Tessera Advanced Technologies, Inc.) (Adeia Inc.)
• Original Assignee: Hitachi, Ltd.
• Inventors: Oroku, Noriyuki, Nishimura, Asao, Minagawa, Madoka, Kanda, Naoya, Hozoji, Hiroshi, Ujiie, Kenji, Yamaguchi, Yoshihide, Yajima, Akira, Tsunoda, Shigeharu, Anjo, Ichiro, Tenmei, Hiroyuki, Inoue, Kosuke
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/698,185
• Time in Patent Office: 1,058 Days
• Field of Search: 257/737, 257/738, 257/781, 257/780, 257/784, 257/701, 257/668
• US Class Current: 257/668
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/295 containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01034 : Selenium [Se]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor apparatus includes a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus. A first electrically insulating layer is formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer. A second electrically insulating layer is formed on said first insulating layer, and external connection terminals are formed on said second insulating layer. A wiring is formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer is formed on said second insulating layer and on said wiring. Particles are provided in the second insulating layer to control a shape of said second insulating layer.

Claims

1. A semiconductor apparatus comprising a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus, a first electrically insulating layer formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer, a second electrically insulating layer formed on said first insulating layer, external connection terminals formed on said second insulating layer, a wiring formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer formed on said second insulating layer and on said wiring, wherein said second insulating layer contains particles to control a shape of said second insulating layer.

2. A semiconductor apparatus according to claim 1, wherein said second insulating layer is a stress relaxation layer to relieve stress caused between said semiconductor device and a board on which the apparatus is to be mounted.

3. A semiconductor apparatus according to claim 1, wherein said particles are made of a same material as that of said second insulating layer.

4. A semiconductor apparatus according to claim 1, wherein said second insulating layer contains particles of an organic material.

5. A semiconductor apparatus according to claim 1, wherein said second insulating layer at least contains particles of an amide-imide resin, of an ester-imide resin, of an ether-imide resin, of a silicone resin, or an acrylic resin, of a polyester resin.

6. A semiconductor apparatus according to claim 1, wherein said second insulating layer has a thickness of from 35 μ

m to 150 μ

m.

7. A semiconductor apparatus according to claim 1, wherein said second insulating layer is a printed layer of an insulating material containing particles, formed by use of a print mask.

8. A semiconductor apparatus comprising a semiconductor device, having circuit electrodes aligned centrally of the semiconductor apparatus, a first electrically insulating layer formed on said semiconductor device, with said circuit electrodes being exposed from said first insulating layer, a second electrically insulating layer formed on said first insulating layer, external connection terminals formed on said second insulating layer, a wiring formed on said second insulating layer to electrically connect said external connection terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer formed on said second insulating layer and on said wiring, wherein said third insulating layer covers an upper surface and a side surface of each of said first insulating layer and said second insulating layer except where said external connection terminals and said wiring are connected to each other.

9. A semiconductor apparatus according to claim 8, wherein said second insulating layer is provided to relax stress produced between the semiconductor apparatus and a substrate on which to mount the apparatus.

10. A semiconductor apparatus according to claim 8, wherein said second insulating layer has a thickness of from 35 μ

m to 150 μ

m.

11. A semiconductor apparatus according to claim 8, wherein said second insulating layer contains particles to controlling a shape of said second insulating layer.

12. A semiconductor apparatus according to claim 8, wherein said second insulating layer includes means for relaxing stress produced between the semiconductor apparatus and a substrate on which to mount the apparatus.

13. A semiconductor apparatus according to claim 8, wherein said second insulating layer has a thickness of from 35 μ

m to 150 μ

m.

14. A semiconductor apparatus according to claim 8, wherein said second insulating layer includes means for controlling a shape of said second insulating layer.

15. A semiconductor apparatus according to claim 14, wherein said means for controlling a shape of said second insulating layer comprises particles included in the second insulating layer.

16. A semiconductor apparatus comprising a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus, a first electrically insulating layer formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer, a second electrically insulating layer formed on said first insulating layer, external connection terminals formed on said second insulating layer, a wiring formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer formed on said second insulating layer and on said wiring, wherein said second insulating layer contains means for controlling a shape of said second insulating layer.

17. A semiconductor apparatus according to claim 16, wherein said means for controlling a shape of said second insulating layer comprises particles formed in said second insulating layer.

18. A semiconductor apparatus according to claim 17, wherein said second insulating layer includes means for relieving stress caused between said semiconductor device and a board on which the apparatus is to be mounted.

19. A semiconductor apparatus according to claim 16, wherein said second insulating layer includes means for relieving stress caused between said semiconductor device and a board on which the apparatus is to be mounted.

20. A semiconductor apparatus according to claim 16, wherein said particles are made of a same material as that of said second insulating layer.

21. A semiconductor apparatus according to claim 16, wherein said second insulating layer contains particles of organic material.

22. A semiconductor apparatus according to claim 16, wherein said second insulating layer at least contains particles of an amide-imide resin, of an ester-imide resin, of an ether-imide resin, of a silicone resin, or an acrylic resin, of a polyester resin.

23. A semiconductor apparatus according to claim 16, wherein said second insulating layer has a thickness of from 35 μ

m to 150 μ

m.

24. A semiconductor apparatus according to claim 16, wherein said second insulating layer is a printed layer of an insulating material containing particles, formed by use of a print mask.