Packaged integrated circuits and methods of producing thereof

• US 6,624,505 B2
• Filed: 01/11/2001
• Issued: 09/23/2003
• Est. Priority Date: 02/06/1998
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Shell Case, Ltd.
• Inventors: Badehi, Avner
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US09/758,906
• Publication Number:
  US 20030080398A1
• Time in Patent Office: 985 Days
• Field of Search: 437/214, 437/678, 257/787, 257/678, 257/621, 257/698, 257/627, 257/82, 438/106, 438/107, 428/699
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/385 : the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

This invention discloses a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.

A method for producing packaged integrated circuits is also disclosed.

Claims

1. A packaged integrated circuit comprising:

an integrated circuit substrate lying in a substrate;

plane and having electrical circuitry formed thereon;

a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane and at least one third surface disposed at an angle to said first and second planar surfaces; and

a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface, at least one individual electrical contact from among said plurality of electrical contacts extending along at least a portion of said at least;

one third surface.

2. A packaged integrated circuit according to claim 1 and wherein said package is a chip-scale package.

3. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

4. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

5. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

6. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

34. A packaged circuit according to claim 1 wherein at least one of said electrical contacts extending onto said first planar surface extends along said at least one third surface.

35. A packaged circuit according to claim 34 wherein at least one of said electrical contacts extending onto said second planar surface extends along said at least one third surface.

36. A packaged circuit according to claim 1 wherein at least one individual electrical contacts from among said plurality of electrical contacts which is connected to said electrical circuitry defines a location of contact between said individual electrical contact and said electrical circuitry and wherein said location of contact is located on said at least one third surface of the package.

37. A packaged circuit according to claim 1 wherein at least a majority of the contacts extend along said at least one third surface.

38. A packaged circuit according to claim 1 wherein substantially all of the contacts extend along said at least one third surface.

7. A packaged integrated circuit assembly comprising:

a packaged integrated circuit including an integrated circuit substrate;

lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing said integrated circuit substrate and defining first and second planar Surfaces generally parallel to said substrate plane, at least one third surface disposed at an angle to said first; and

second planar surfaces and a plurality of electrical contacts, each connected to said electrical circuitry at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface, at least one individual electrical contact from among said plurality of electrical contacts extending along at least a portion of said at least one third surface; and

at least one additional electrical circuit element mounted onto and supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.

8. A packaged integrated circuit assembly according to claim 7 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of:

passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.

9. A packaged integrated circuit according to claim 7 and wherein said package is a chip-scale package.

10. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

11. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

12. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

13. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

14. A method for producing packaged integrated Circuits comprising:

producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;

providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane and at least one third surface disposed at an angle to said first and second planar surfaces;

forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface, at least one individual electrical contact from among said plurality of electrical contacts extending along at least a portion of said at least one third surface; and

separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip pack-7gos.

15. A method for producing packaged integrated circuits according to claim 14 and wherein said plurality of individual chip packages are chip scale packages.

16. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

17. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

18. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

19. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

20. A method for producing packaged integrated circuit assemblies, the method comprising:

producing, on a wafer scale, an integrated circuit substrate lying in a substrata plane and having electrical circuitry formed thereon;

providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane and at least one third surface disposed at an angle to said first and second planar surfaces;

forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at leapt some of said plurality of electrical contacts extending onto said;

First planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface, at least one individual electrical contact from among said plurality of electrical contacts extending along at least a portion of said at least one third surface;

separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chap packages; and

subsequently mounting onto said at second planar surface of at least one of said plurality of individual chip packages, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported key said second planar surface and electrically coupled to at least;

one of said plurality of electrical contacts extending therealong.

21. A method of forming a packaged integrated circuit assembly according to claim 20 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of:

passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.

22. A method for producing packaged integrated circuits according to claim 20 and wherein said plurality of individual chip packages are chip scale packages.

23. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

24. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

25. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

26. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

27. A method for producing packaged integrated circuit:

assemblies, the method comprising;

producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;

providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane and at least one third surface disposed at an angle to said first and second planar surface;

forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface, at least one individual electrical contact from among said plurality of electrical contacts extending along at least a portion of said at least one third surface;

mounting onto said at second planar surface of said wafer scale packaging, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong; and

subsequently separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual, chip packages.

28. A method of forming a packaged integrated circuit assembly according to claim 27 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of:

passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.

29. A method for producing packaged integrated circuits according to claim 27 and wherein said plurality of individual chip packages are chip scale packages.

30. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

31. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.

32. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.

33. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.