Digitally programmable phase-lock loop for high-speed data communications

• US 6,624,668 B1
• Filed: 11/06/2001
• Issued: 09/23/2003
• Est. Priority Date: 11/08/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Gaboury, Michael J., Robinson, Moises E., Grung, Bernard L.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US10/005,736
• Time in Patent Office: 686 Days
• Field of Search: 327/103, 327/50-53, 327/63-66, 327/427, 327/519, 327/520, 327/538, 327/543, 327/560-563, 327/576, 327/581, 323/315, 330/252-255, 330/257, 330/261, 330/277, 330/278, 330/284, 330/288
• US Class Current: 327/103
• CPC Class Codes: H03L 2207/04 Modifications for maintaining constant the phase-locked loop damping factor when other loop parameters change
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices. Accordingly, the present inventors devised a digitally programmable phase-lock loop which operates at a frequency selected from a set of two of more frequencies. One such phase-lock loop includes a charge pump, a loop filter, and a voltage-controlled oscillator, all of which are programmable to control the operating frequency of the phase-lock loop and thus devices, such as receivers, transmitters, and transceivers incorporating it. Moreover, the programmability of these three components enables the exemplary embodiment to maintains a constant damping factor and a constant ratio of input frequency to loop bandwidth for each frequency setting, thereby promoting loop stability and rapid settling at each selected frequency.

Claims

1. A transconductor that generates an output current as a function of a first and a second input voltage, comprising:

an input stage that accepts said first and said second input voltages and generates a first and a second current;

a first current mirror having an input terminal and an output terminal, said input terminal accepting said first current;

a second current mirror having an input terminal coupled to said output terminal of said first current mirror and further having an output terminal;

a third current mirror having an input terminal and an output terminal, said input terminal accepting said second current;

a control circuit for controlling mode of operation of said input stage, said first current mirror, said second current mirror, and said third current mirror;

a programmable gain control circuit that controls gains of said second and said third current mirrors;

wherein said output terminals of said second and said third current mirrors are coupled to generate said output current.

2. The transconductor of claim 1 wherein each of said second and said third current mirrors comprises a circuit for increasing output impedance.

3. The transconductor of claim 1 wherein said mode of operation comprises a standby mode and a normal mode.

4. The transconductor of claim 3 further comprising a circuit for generating DC operating point of said input stage, said first current mirror, said second current mirror, and said third current mirror, wherein said control circuit causes said DC operating point to be at a first point when said mode of operation is at said normal mode and at a second point when said mode of operation is at said standby mode.

5. The transconductor of claim 4 wherein said control circuit controls biasing current that generates said DC operating point.

6. The transconductor of claim 1 wherein said mode of operation comprises a power down mode.

7. The transconductor of claim 1 further comprising a circuit to reduce power supply noise.

8. The transconductor of claim 1 further comprising a circuit to reduce common mode noise.

9. The transconductor of claim 1 wherein said input stage has a first transconductance value, wherein said transconductor has a second transconductance value, and wherein said first transconductance value is larger than said second transconductance value.

10. The transconductor of claim 1 herein each of said second and said third current mirrors contains at least a first and a second current path, and said gain control circuit turning said second current path on or off in response to a program signal.

11. The transconductor of claim 1 wherein said gain control circuit comprises at least one switching transistor.

12. The transconductor of claim 1 herein said gains of said second and said third current mirrors are less than one.

13. The transconductor of claim 1 wherein product of gain of said first and said second current mirrors is substantially same as gain of said third current mirror.

14. A programmable phase-locked loop, comprising:

a first loop; and

a second loop coupled to the first loop comprising a programmable transconductor that generates an output current as a function of a first and a second input voltage, wherein the transconductor comprises;

an input stage that accepts said first and said second input voltages and generates a first and a second current;

a first current mirror having an input terminal and an output terminal, said input terminal accepting said first current;

a second current mirror having an input terminal coupled to said output terminal of said first current mirror and further having an output terminal;

a third current mirror having an input terminal and an output terminal, said input terminal accepting said second current;

a control circuit for controlling mode of operation of said input stage, said first current mirror, said second current mirror, and said third current mirror; and

a programmable gain control circuit that controls gains of said second and said third current mirrors;

wherein said output terminals of said second and said third current mirrors are coupled to generate said output current.

15. The programmable phase-locked loop of claim 14, wherein the second loop further comprises a phase detector, coupled to the programmable transconductor, wherein the programmable transconductor is further coupled to a programmable voltage-controlled oscillator.

16. The programmable phase-locked loop of claim 15, wherein the first loop comprises the programmable voltage-controlled oscillator, a programmable charge pump, and a programmable loop filter.

17. The programmable phase-locked loop of claim 16, wherein the first loop further comprises a frequency divider and a phase-frequency detector coupled between the programmable voltage-controlled oscillator and the programmable charge pump.

18. The programmable phase-locked loop of claim 16, wherein the programmable voltage-controlled oscillator, the programmable charge pump, the programmable loop filter and the programmable transconductor are controlled by a single program signal.