False target radar image generator for countering wideband imaging radars

• US 6,624,780 B1
• Filed: 10/02/2002
• Issued: 09/23/2003
• Est. Priority Date: 10/02/2002
• Status: Active Grant

• Current Assignee: United States Secretary of the Navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Fouts, Douglas Jai, Pace, Phillip E.
• Primary Examiner(s): Sotomayor, John B.
• Application Number:
  US10/267,094
• Time in Patent Office: 356 Days
• Field of Search: 342/13, 342/14, 342/15, 342/25, 342/194, 342/195
• US Class Current: 342/14
• CPC Class Codes: G01S 13/90 using synthetic aperture techniques , e.g. synthetic aperture radar [SAR] techniques
• CPC Class Codes: G01S 13/9064 Inverse SAR [ISAR]
• CPC Class Codes: G01S 7/021 Auxiliary means for detecting or identifying radar signals or the like, e.g. radar jamming signals
• CPC Class Codes: G01S 7/38 Jamming means, e.g. producing false echoes

Abstract

A system for generating a false target radar image for countering wideband synthetic aperture and inverse synthetic aperture imaging radar systems to prevent a selected target from being detected by such radar systems comprises a receiver system for producing a digital signal that represents an incident radar signal. A phase sampling circuit is connected to the receiver for sampling the digital signal and providing phase sample data. An image synthesizer circuit is connected to the phase sampling circuit and arranged to receive the phase sample data therefrom. The digital image synthesizer circuit is arranged to process the phase sample data to form a false target signal, which is input to a signal transmitter system arranged to transmit the synthesized false target signal so that it can be received by a radar system.

Claims

1. A system for generating a false target radar image for countering wideband synthetic aperture and inverse synthetic aperture imaging radar systems, comprising:

a receiver system for producing a signal that represents an incident radar signal;

a phase sampling circuit connected to the receiver for sampling the received signal and providing phase sample data;

an image synthesizer circuit connected to the phase sampling circuit and arranged to receive the phase sample data therefrom, the digital image synthesizer circuit being arranged to process the phase sample data to form a false target signal; and

a signal transmitter system arranged to transmit the synthesized false target signal so that it can be received by a radar system.

2. The system of claim 1 wherein the receiver system comprises:

a radar receiver for producing an output signal in response to a received wideband chirp signal;

a down converter connected to the radar receiver; and

an oscillator connected to the down converter for providing a reference signal thereto, the down converter being arranged to process the reference signal and the wide-band chirp signal to produce a signal component I that is in phase and a component Q that is in quadrature with the wide-band chirp signal, wherein the phase sampling circuit comprises a phase sampling digital radio frequency memory connected to the down converter to receive the signals I and Q therefrom.

3. The system of claim 2 wherein the image synthesizer circuit is arranged to calculate numerical values of in-phase and quadrature components of the false target signal.

4. The system of claim 2 wherein the transmitter system comprises:

a pair of digital to analog converters connected to the image synthesizer circuit and arranged to produce analog signal components corresponding to the false target in-phase and quadrature digital image signal components;

an up converter connected to the pair of digital to analog converters and to the local oscillator, the up converter being arranged to convert the analog signals from the digital to analog converters to an RF signal appropriate for amplification and transmission so that it can be received by a radar system.

5. The system of claim 4 wherein the image synthesizer circuit comprises a linear array of range bin processors arranged to calculate numerical values for the false target in-phase and quadrature digital image signals.

6. The system of claim 5 wherein phase samples from the digital radio frequency memory are simultaneously input to every range bin processor in the linear array without any delay between the range bin processors.

7. The system of claim 5 further comprising a microprocessor arranged to control the image synthesizer circuit.

8. The system of claim 7, further comprising a plurality of summation adders arranged to create the delays required between the range bin processors.

9. The system of claim 7 wherein each of said range bins comprises:

a phase rotation adder having inputs connected to the microprocessor and to the phase sampling digital radio frequency memory, the phase rotation adder being arranged to add phase rotation data received from the microprocessor to phase samples received from the phase sampling digital radio frequency memory to produce a phase rotation angle signal;

a read only memory arranged to receive the phase rotation signal from the phase rotation adder and provide output signals that indicate the sine and cosine of the phase rotation angle;

a first summation adder arranged to add the sine signal to a partial Q summation of sine signals from the next range bin processor in the linear array and produce a new partial Q summation that is input to the next range bin processor in the array; and

a second summation adder arranged to add the cosine signal to a partial I summation of cosine signals from the previous range bin processor in the linear array and produce a new partial I summation that is input to the next range bin processor in the array.

10. The system of claim 9, further comprising:

a phase rotation buffer connected to the microprocessor to receive the phase rotation data therefrom;

a phase rotation register connected between the phase rotation buffer and the phase rotation adder; and

wherein the phase rotation buffer and the phase rotation register are controlled such that new phase increment values can be loaded into the phase rotation buffer from the control microprocessor without affecting the phase rotation value in the phase rotation register and such that calculations using the value in the phase rotation register are allowed to proceed with out interruption and such that the new phase rotation value in the phase rotation buffer is allowed to be loaded into the phase rotation register with a single clock and to be loaded synchronously with the loading of all phase rotation registers and all gain registers in all range bin processors.

11. The system of claim 9, further comprising:

a gain buffer connected to the microprocessor to receive gain data therefrom;

a gain register connected to the gain buffer;

wherein the gain buffer and the gain register are controlled such that new gain values can be loaded into the gain buffer from the control microprocessor without affecting the gain value in the gain register, and allowing calculations using the value in the gain register to proceed without interruption, and allowing the new gain value in the gain buffer to be loaded into the gain register with a single clock and to be loaded synchronously with the loading of all gain registers and all phase rotation registers in all range bin processors;

a first gain multiplier arranged to receive the sine signal as a first input and a signal output from the gain register as a second input, the gain multiplier being further arranged to provide the sine signal to the summation adder; and

a second gain multiplier arranged to receive the cosine signal as a first input and a signal output from the gain register as a second input, the gain multiplier being further arranged to provide the sine signal to the summation adder.

12. The system of claim 9, further comprising a pipelined array of adders arranged to sum signals output from all of the range bins.

13. A method for generating a false target radar image for countering wideband synthetic aperture and inverse synthetic aperture imaging radar systems comprising:

connecting a receiving antenna and a down-converting-receiver to a phase-sampling circuit to provide phase sample data;

connecting an image synthesizer circuit to the phase sampling circuit;

arranging the image synthesizer circuit to process the phase sample data to form a false target signal; and

transmitting the synthesized false target signal so that it can be received by a radar system.

14. The method of claim 13, further comprising the steps of:

arranging a radar receiver for receiving a wide-band chirp signal;

connecting the radar receiver to a down-converter;

connecting an oscillator to the down converter for providing a reference signal thereto;

arranging the down converter to process the reference signal and the wide-band chirp signal to produce a signal component I that is in phase with, and a component Q that is in quadrature with, the wideband chirp signal; and

forming the phase sampling circuit to comprise a phase sampling digital radio frequency memory connected to the down converter to receive the signals I and Q therefrom.

15. The method of claim 13 further comprising the step of arranging the image synthesizer circuit to calculate numerical values of in-phase and quadrature components of the false target signal.

16. The method of claim 13 further comprising the steps of:

connecting a pair of digital to analog converters connected to the image synthesizer circuit;

arranging the pair of digital to analog converters to produce analog signal components corresponding to the false target in-phase and quadrature digital image signal components;

connecting an up converter to the pair of digital to analog converters and to the local oscillator;

arranging the up converter to convert the analog signal components into an RF signal for transmission; and

providing a signal transmitter arranged to transmit the RF signal so that it can be received by a radar system.

17. The method of claim 16 further comprising the step of forming the image synthesizer circuit to comprise a linear array of range bins arranged to calculate numerical values for the false target in-phase and quadrature digital image signals.

18. The method of claim 17 further comprising the step of providing a microprocessor arranged to control the image synthesizer circuit.

19. The method of claim 18 further comprising the steps of:

providing a phase rotation adder having inputs connected to the microprocessor and to the phase sampling digital radio frequency memory;

arranging the phase rotation adder to add phase rotation data received from the microprocessor to phase samples received from the phase sampling digital radio frequency memory to produce a phase rotation angle signal;

providing a read only memory arranged to receive the phase rotation signal from the phase rotation adder and provide output signals that indicate the sine and cosine of the phase rotation angle;

adding the sine signal to a partial Q summation of sine signals from the previous range bin in the linear array and produce a new partial Q summation that is input to the next range bin in the array; and

adding the cosine signal to a partial I summation of cosine signals from the previous range bin in the linear array and produce a new partial I summation that is input to the next range bin in the array.

20. The method of claim 19, further comprising the steps of:

connecting a phase rotation buffer to the microprocessor to receive the phase rotation data therefrom; and

connecting a phase rotation register between the phase rotation buffer and the phase rotation adder.

21. The method of claim 19, further comprising the steps of:

connecting a gain buffer to the microprocessor to receive gain data therefrom;

connecting a gain register to the gain buffer;

arranging a first gain multiplier to receive the sine signal as a first input and a signal output from the gain register as a second input;

arranging the gain multiplier to provide the sine signal to the summation adder;

arranging a second gain multiplier to receive the cosine signal as a first input and a signal output from the gain register as a second input; and

arranging the gain multiplier to provide the sine signal to the summation adder.