Semiconductor memory device adaptable to various types of packages

• US 6,625,050 B2
• Filed: 05/14/2002
• Issued: 09/23/2003
• Est. Priority Date: 10/29/2001
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yonetani, Hideki, Nagasawa, Tsutomu, Yamauchi, Tadaaki, Matsumoto, Junko, Suwa, Makoto, Jinbo, Shinichi, Tian, Zengcheng, Okamoto, Takeo, Ishida, Kozo
• Primary Examiner(s): Dinh, Son T.
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US10/143,931
• Publication Number:
  US 20030081443A1
• Time in Patent Office: 497 Days
• Field of Search: 365/51, 365/63, 365/230.03, 365/226, 365/205, 365/207, 365/189.08, 365/189.11
• US Class Current: 365/63
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.

Claims

1. A semiconductor memory device rectangular in shape and adaptable to various types of packages, comprising:

a memory element storing externally supplied data; and

a plurality of bonding pads for conveying power supply, data and a signal to/from said memory element, wherein

said plurality of bonding pads includes a first power supply pad and a first ground pad and other bonding pads except for said first power supply pad and said first ground pad,

said first power supply pad and said first ground pad are placed near the center of each of two opposite sides of said semiconductor memory device, and

said other bonding pads including a second power supply pad and a second ground pad are arranged on a peripheral region along remaining two sides other than said two opposite sides.

2. The semiconductor memory device according to claim 1, wherein when said semiconductor memory device is packaged by a TSOP, said first power supply pad is used by being wired to a lead of a leadframe that provides external power supply and said first ground pad is used by being wired to a lead of the leadframe that is grounded, and

when said semiconductor memory device is packaged by a BGA package or multichip package, said second power supply pad is used by being wired to a lead of the leadframe that provides external power supply and said second ground pad is used by being wired to a lead of the leadframe that is grounded.

3. The semiconductor memory device according to claim 1, wherein

said semiconductor memory device has its word structure switchable between a first word structure and a second word structure larger than said first word structure, and

when said semiconductor memory device is used for said first word structure, said second power supply pad and said second ground pad are used by being wired respectively to a lead of a leadframe that provides external power supply and a lead of the leadframe that is grounded and

when said semiconductor memory device is used for said second word structure, said first power supply pad and said first ground pad are used by being wired respectively to a lead of the leadframe that provides external power supply and a lead of the leadframe that is grounded.

4. The semiconductor memory device according to claim 3, wherein

said second power supply pad and said second ground pad are each placed at an outermost end of a line of the bonding pads arranged along each of said remaining two sides.

5. The semiconductor memory device according to claim 1, further comprising:

a first voltage downconverter circuit converting an external power supply potential provided from said first power supply pad to an internal power supply potential; and

a second voltage downconverter circuit converting an external power supply potential provided from said second power supply pad to an internal power supply potential, wherein

said first voltage downconverter circuit is placed near said first power supply pad and said first ground pad, and

said second voltage downconverter circuit is placed near said second power supply pad and said second ground pad.

6. The semiconductor memory device according to claim 5, wherein

said first voltage downconverter circuit is activated when said semiconductor memory device is packaged by a TSOP, and

said second voltage downconverter circuit is activated when said semiconductor memory device is packaged by a BGA package or multichip package.

7. The semiconductor memory device according to claim 5, wherein

said first voltage downconverter circuit and said second voltage downconverter circuit each include

an internal power supply node providing the internal power supply potential to internal circuitry of said semiconductor memory device,

an external power supply node provided with the external power supply potential and

an internal power supply generating circuit converting said external power supply potential to said internal power supply potential and providing said internal power supply, potential to said internal power supply node,

said semiconductor memory device has its word structure switchable between a first word structure and a second word structure larger than said first word structure, and

when said semiconductor memory device is used for said first word structure, said internal power supply generating circuit reduces an amount of current provided from said external power supply node to said internal power supply node.

8. The semiconductor memory device according to claim 7, wherein

said internal power supply generating circuit includes

a differential amplifier circuit amplifying a potential difference between said internal power supply potential and a reference potential which is a target potential of said internal power supply potential and outputting a potential level corresponding to the amplified potential difference,

a driving circuit providing current from said external power supply node to said internal power supply node via a plurality of nodes according to the potential level output from said differential amplifier circuit, and

a switching circuit changing ability of said driving circuit by cutting off current through at least one of said plurality of nodes to reduce current provided by said driving circuit to said internal power supply node when said semiconductor memory device is used for said first word structure.

9. The semiconductor memory device according to claim 7, wherein

said internal power supply generating circuit includes

a differential amplifier circuit amplifying a potential difference between said internal power supply potential and a reference potential which is a target potential of said internal power supply potential and outputting a potential level corresponding to the amplified potential difference,

a driving circuit providing current from said external power supply node to said internal power supply node according to the potential level output from said differential amplifier circuit, and

a switching circuit changing ability of said differential amplifier circuit by raising the potential level output from said differential amplifier circuit to reduce current provided by said driving circuit to said internal power supply node when said semiconductor memory device is used for said first word structure.

10. The semiconductor memory device according to claim 7, further comprising a power-on circuit generating, after external power supply is provided, an activation signal until said internal power supply potential reaches a predetermined potential, wherein

said semiconductor memory device includes at least one second voltage downconverter circuit,

said power-on circuit is connected to at least one of said second voltage downconverter circuits, and

said second voltage downconverter circuit connected to said power-on circuit increases, according to said activation signal provided from said power-on circuit, an amount of current provided from said external power supply node to said internal power supply node.

11. The semiconductor memory device according to claim 5, wherein

said first voltage downconverter circuit provides power supply for a memory cell array and is placed under an internal power supply line placed along the outer periphery of said semiconductor memory device.

12. The semiconductor memory device according to claim 1, wherein

a plurality of bonding pads placed on each end of a line of the bonding pads arranged along each of said remaining two sides are arranged in reverse order relative to an order of pins of a package in which said semiconductor memory device is encapsulated.

13. The semiconductor memory device according to claim 12, wherein

the line of the bonding pads arranged along each of said remaining two sides includes at least one pair of a third power supply pad and a third ground pad used for a first word structure and at least one pair of a fourth power supply pad and a fourth ground pad used for a second word structure larger than said first word structure,

the pair of said third power supply pad and said third ground pad and the pair of said fourth power supply pad and said fourth ground pad are each placed on said end of the line of the bonding pads arranged along each of said remaining two sides,

said third power supply pad and said third ground pad are arranged in the same order as the order of pins of the package in which said semiconductor memory device is encapsulated, and

said fourth power supply pad and said fourth ground pad are arranged in reverse order relative to the order of pins of the package in which said semiconductor memory device is encapsulated.

14. The semiconductor memory device according to claim 1, wherein

said memory element includes

a memory cell array having a plurality of memory cells,

an input/output circuit connected to a data input/output pad included in said bonding pads for input/output of data from/to external circuitry, and

a data bus for transmitting data between said memory cell array and said input/output circuit,

said memory cell array is formed of four banks arranged respectively in four regions of said semiconductor memory device, said four regions corresponding to respective regions generated by dividing said semiconductor memory device along a vertical central line and a horizontal central line,

said input/output circuit is placed on the peripheral region along said remaining two sides where a line of said bonding pads is placed,

said data bus is placed between said banks and along said remaining two sides, and

said banks are each connected to said data bus placed on a central region between said banks and extending in parallel with said remaining two sides.

15. The semiconductor memory device according to claim 14, further comprising an equalize circuit setting potential on said data bus at a predetermined potential for a predetermined period, wherein

at least one said equalize circuit is placed on a data path along said data bus connecting said input/output circuit and each of said banks.

16. The semiconductor memory device according to claim 1, wherein

said memory element includes

a memory cell array having a plurality of memory cells,

an input/output circuit connected to a data input/output pad included in said bonding pads for input/output of data from/to external circuitry, and

a data bus for transmitting data between said memory cell array and said input/output circuit,

said memory cell array is formed of four banks arranged respectively in four regions of said semiconductor memory device, said four regions corresponding to respective regions generated by dividing said semiconductor memory device along a vertical central line and a horizontal central line,

said input/output circuit is placed on the peripheral region along said remaining two sides where a line of said bonding pads is placed,

said data bus is placed along a central line which is in parallel with said remaining two sides of said semiconductor memory device and along said two sides and said remaining two sides, and

said banks are each connected to said data bus placed between said banks and extending in parallel with said remaining two sides.

17. The semiconductor memory device according to claim 1, wherein

said memory element includes

a memory cell array having a plurality of memory cells,

an input/output circuit connected to a data input/output pad included in said bonding pads for input/output of data from/to external circuitry, and

a data bus for transmitting data between said memory cell array and said input/output circuit,

said memory cell array has a hierarchical I/O structure and is formed of four banks arranged respectively in four regions of said semiconductor memory device, said four regions corresponding to respective regions generated by dividing said semiconductor memory device along a vertical central line and a horizontal central line,

said input/output circuit is placed on the peripheral region along said remaining two sides where a line of said bonding pads is placed,

said data bus is placed along a central line which is in parallel with said two sides of said semiconductor memory device and along said remaining two sides, and

said banks are each connected to said data bus placed between said banks and extending in parallel with said two sides.

18. The semiconductor memory device according to claim 1, wherein

said memory element includes

a memory cell array having a plurality of memory cells and

voltage downconverter circuits converting an external power supply potential provided from said first power supply pad to an internal power supply potential for providing power supply to said memory cell array, wherein

said voltage downconverter circuits are each small in size and placed on each sense amplifier band on said memory cell array, and

said external power supply potential is provided from said first power supply pad through a first external power supply line connected to said first power supply pad and placed along each of said two sides and through a plurality of second power supply lines connected to said first external power supply line and placed on said memory cell array.

19. A semiconductor memory device having a switchable internal power supply voltage and a switchable interface voltage, comprising:

a first switch signal generating circuit generating a first switch signal for switching said internal power supply voltage;

a second switch signal generating circuit generating a second switch signal for switching said interface voltage;

an internal power supply generating circuit converting, according to said first switch signal, an external power supply voltage to a predetermined internal power supply voltage and outputting the predetermined internal power supply voltage to an internal power supply node; and

an input circuit changing, according to said second switch signal, a threshold of voltage determining a logic level of an external input signal,

said first switch signal generating circuit including a first bonding pad and generating said first switch signal according to whether or not a wire provided with a predetermined potential is connected to said first bonding pad, and

said second switch signal generating circuit including a second bonding pad and generating said second switch signal according to whether or not a wire provided with a predetermined potential is connected to said second bonding pad.

20. The semiconductor memory device according to claim 19, wherein

said first switch signal generating circuit further includes a first fuse connected to a node coupled to said first bonding pad and connected to the internal power supply node,

said first switch signal generating circuit generates said first switch signal according to whether or not said first fuse is laser-blown, and generates, when said first fuse is mistakenly blown, said first switch signal according to whether or not a wire provided with a predetermined potential is connected to said first bonding pad,

said second switch signal generating circuit further includes a second fuse connected to a node coupled to said second bonding pad and connected to the internal power supply node,

said second switch signal generating circuit generates said second switch signal according to whether or not said second fuse is laser-blown, and generates, when said second fuse is mistakenly blown, said second switch signal according to whether or not a wire provided with a predetermined potential is connected to said second bonding pad.