Policy engine architecture
First Claim
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1. A policy engine comprising:
- a stream classification module;
a packet input/output module that places received packets in an external packet memory and that notifies the stream classification module of the packets in the external packet memory;
wherein the stream classification module creates a packet service header for each packet in the external packet memory indicating, based on a policy cache, policies to be enforced on that packet;
a policy enforcement module to enforce policies on the packets, including a packet scheduler that fragments each packet into cells and schedules enforcement of the policies on each cell based on the packet service header;
on-chip packet buffer circuitry to temporarily hold the packets during policy enforcement; and
a plurality of action processors, each action processor performing a particular policy enforcement on a cell and routing the cell to a next one of the action processors.
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Abstract
A policy engine for handling incoming data packets. The policy engine includes a stream classification module, a data packet input/output module, and a policy enforcement module. The policy enforcement module further includes a packet scheduler, an on-chip packet buffer circuitry, and a plurality of action processors. The stream classification module creates a packet service header for each data packet, wherein the packet service header indicates policies to be enforced for that data packet. The action processors enforce the policies.
185 Citations
1 Claim
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1. A policy engine comprising:
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a stream classification module;
a packet input/output module that places received packets in an external packet memory and that notifies the stream classification module of the packets in the external packet memory;
wherein the stream classification module creates a packet service header for each packet in the external packet memory indicating, based on a policy cache, policies to be enforced on that packet;
a policy enforcement module to enforce policies on the packets, including a packet scheduler that fragments each packet into cells and schedules enforcement of the policies on each cell based on the packet service header;
on-chip packet buffer circuitry to temporarily hold the packets during policy enforcement; and
a plurality of action processors, each action processor performing a particular policy enforcement on a cell and routing the cell to a next one of the action processors.
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Specification
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Current AssigneeWatchGuard Technologies Incorporated (Gladiator Corporation)
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Original AssigneeWatchGuard Technologies Incorporated (Gladiator Corporation)
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InventorsYu, JungJi John
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Primary Examiner(s)Vanderpuye, Kenneth
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Assistant Examiner(s)Phunkulh, Bob A.
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Application NumberUS09/464,939Time in Patent Office1,377 DaysField of Search370/229, 370/230, 370/230.1, 370/231, 370/235, 370/389, 370/392, 370/400, 370/401, 370/419, 370/428, 370/429, 709/238, 713/153, 713/154US Class Current370/389CPC Class CodesH04L 47/10 Flow control; Congestion co...H04L 47/20 Traffic policingH04L 47/2441 relying on flow classificat...
