Smart DC offset correction loop

• US 6,625,232 B1
• Filed: 05/22/2000
• Issued: 09/23/2003
• Est. Priority Date: 05/22/2000
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Tilley, Keith A.
• Primary Examiner(s): Ghayour, Mohammad H.
• Application Number:
  US09/575,271
• Time in Patent Office: 1,219 Days
• Field of Search: 375/319, 375/316, 375/317, 375/318, 375/243, 375/286, 375/345
• US Class Current: 375/319
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A DC offset correction method and apparatus. In a differential system, a DC offset correction loop includes a gain stage (104) having a differential input, a gain G and a differential output. A DAC circuit (130) provides a correction DC signal at the inputs to produce differential output signals V_o′ and {overscore (V_o)}′. A controller (120) corrects the DC offset by stepping the DAC circuit (130) to change the correction DC signal by an amount equal to approximately (V_o′−{overscore (V_o′)})/G_x, where G_X is the gain G times the gain of the DAC expressed in volts per DAC step. A similar algorithm can be applied to single ended systems wherein a single ended V_OFFSET is corrected by an amount equal to approximately V_OFFSET/G_x.

Claims

1. A method for correcting a DC offset in a differential electronic circuit, comprising:

providing a gain stage having a differential input, a gain G and a differential output;

providing a Digital to Analog Converter (DAC);

defining a gain G_X as gain G times a gain of the DAC;

examining differential output signals V_o′

and {overscore (V_o)}′

; and

correcting the DC offset by applying a correction DC signal from the DAC equal to approximately (V_o′

−

{overscore (V_o)}′

)/G_X at the differential input.

2. A method in accordance with claim 1, wherein the method is carried out in one of a radio transmitter and a radio receiver.

3. A method in accordance with claim 1, further comprising providing an Analog to Digital Converter (ADC) which converts the signals V_o and {overscore (V_o)}into digital form for processing by a controller.

4. A method in accordance with claim 1, further comprising reporting an error in the event of any of the following conditions:

the DAC is set at its minimum or maximum setting;

the DAC is toggling between two values on successive iterations; and

an iteration limit is reached.

5. A method in accordance with claim 1, further comprising determining if |V_o′

−

{overscore (V_o)}′

| is less than a specification value, and if |V_o′

−

{overscore (V_o)}′

| is less than a specification value then fixing the correction DC signal.

6. A method in accordance with claim 1, further comprising calculating a refined value for G_X as:

G_X=(a change in V₀′

−

{overscore (V_o)}′

)/(a number of DAC steps).

7. A method in accordance with claim 6, further comprising determining if |V_o′

−

{overscore (V_o)}′

| is less than a specification value, and if |V_o′

−

{overscore (V_o)}′

| is not less than a specification value then again correcting the DC offset by changing the correction DC signal by an amount equal to approximately (V_o′

−

{overscore (V_o)}′

)/ (the refined value of G_X).

8. A method in accordance with claim 1, further comprising disabling an AC component of the differential input.

9. A method for correcting a DC offset in an electronic circuit, comprising:

providing a gain stage having an input, a gain G and an output;

providing a Digital to Analog Converter (DAC) which sets a correction DC signal;

defining a gain G_X as gain G times a gain of the DAC;

determining an amount of DC offset signal V_OFFSET at the output; and

correcting the DC offset by applying the correction DC signal at the input by moving the DAC by an integer number of steps approximating (V_OFFSET)/G_X.

10. A method in accordance with claim 9, wherein the method is carried out in one of a radio transmitter and a radio receiver.

11. A method in accordance with claim 9, further comprising reporting an error in the event of any of the following conditions:

the DAC is set at its minimum or maximum setting;

the DAC is toggling between two values on successive iterations; and

an iteration limit is reached.

12. A method in accordance with claim 9, further comprising providing an Analog to Digital Converter (ADC) which converts V_OFFSET into digital form for processing by a controller.

13. A method in accordance with claim 9, further comprising determining if |V_OFFSET | is less than a specification value, and if |V_OFFSET | is less than a specification value then fixing the correction DC signal.

14. A method in accordance with claim 9, further comprising calculating a refined value for G_X as:

G_X=a change in V_OFFSET/(a number of DAC steps).

15. A method in accordance with claim 14, further comprising determining if |V_OFFSET | is less than a specification value, and if |V_OFFSET | is not less than a specification value then again correcting the DC offset by changing the correction DC signal by an amount equal to approximately (V_OFFSET)/(the refined value of G_X).

16. A method in accordance with claim 9, further comprising disabling an AC component of the input.