Method and apparatus for dynamically defining line buffer configurations

• US 6,625,708 B1
• Filed: 11/23/1999
• Issued: 09/23/2003
• Est. Priority Date: 11/23/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lam, Fong-Shek
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/447,536
• Time in Patent Office: 1,400 Days
• Field of Search: 710/52, 710/56, 710/104, 710/310, 711/129, 711/153, 711/154, 711/156, 711/170, 711/171, 711/172, 711/173, 711/209
• US Class Current: 711/170
• CPC Class Codes: G06T 1/60 Memory management

Abstract

A method and apparatus of defining a line buffer configuration in a memory is disclosed. In one embodiment, the method and apparatus receives input data information and mode information, proceeds to select a type of the line buffer configuration according to the mode information, and dynamically generates addresses for the selected type of line buffer configuration in the memory according to the input data information.

Claims

1. A method of defining a line buffer configuration in a memory, comprising:

receiving input data information and mode information;

selecting the type of the line buffer configuration according to the mode information; and

dynamically generating addresses for the selected type of line buffer configuration in the memory according to the input data information,

wherein the dynamically generating further comprises incrementing the generated addresses by a pre-determined offset when;

the mode information indicates the type of line buffer configuration, which uses a higher half and a lower half of the memory; and

the generated addresses exceed address ranges of the lower half.

2. The method according to claim 1, wherein the input data information further comprises data format information and data size information, and the mode information indicates a type of line buffer configuration.

3. The method according claim 2, wherein the dynamically generating further comprises:

generating a lowest available address for the line buffer configuration; and

generating a highest available address for the line buffer configuration according to the data size information and the lowest available address.

4. The method according to claim 3, wherein the dynamically generating further comprises generating a mid-point address for the line buffer configuration according to the highest available address.

5. The method according to claim 1, wherein the memory is a Static Random Access Memory (SRAM) and is segmented into a higher half and a lower half.

6. The method according to claim 5, wherein addresses of the higher half have ones as their most significant bits (MSBs), and addresses of the lower half have zeroes as their MSBs.

7. The method according to claim 1, wherein the input data information comprises planar and packed video data.

8. The method according to claim 1, wherein the addresses generated further comprise write addresses and read addresses.

9. An apparatus for defining a line buffer configuration in a memory, comprising:

a boundary generator to receive input data information and to generate a lowest available and a highest available addresses for the line buffer configuration according to the input data information; and

a line buffer address generator, coupled to the boundary generator, to receive mode information and to dynamically generate read and write addresses to the memory according to the mode information and output from the boundary generator,

wherein the line buffer address generator further comprises incrementing the read and write addresses by a pre-determined offset when;

the mode information indicates the type of line buffer configuration, which uses a higher half and a lower half of the memory; and

either the read or the write addresses exceed address ranges of the lower half.

10. The apparatus according to claim 9, wherein the input data information further comprises data format information and data size information, and the mode information indicates a type of line buffer configuration.

11. The apparatus according claim 10, wherein the boundary generator generates the highest available address according to the data size information and the lowest available address.

12. The apparatus according to claim 10, wherein the boundary generator further generates a mid-point address for the line buffer configuration according to the highest available address.

13. The apparatus according to claim 9, wherein the memory is a Static Random Access Memory (SRAM) and is segmented into a higher half and a lower half.

14. The apparatus according to claim 13, wherein addresses of the higher half have ones as their most significant bits (MSBs), and addresses of the lower half have zeroes as their MSBs.

15. The apparatus according to claim 9, wherein the input data information comprises planar and packed video data.

16. An electronic system for defining a line buffer configuration in a memory, comprising:

a processor bus coupled to the memory; and

a plurality of microprocessors, coupled to the processor bus wherein the plurality of microprocessors further comprises;

a boundary generator to receive input data information and to generate a lowest available and a highest available addresses for the line buffer configuration according to the input data information; and

a line buffer address generator, coupled to the boundary generator, to receive mode information and to generate read and write addresses to the memory according to the mode information and output from the boundary generator,

wherein the line buffer address generator further comprises incrementing the read and write addresses by a pre-determined offset when;

the mode information indicates the type of line buffer configuration, which uses a higher half and a lower half of the memory; and

either the read or the write addresses exceed address ranges of the lower half.

17. The electronic system according to claim 16, wherein the input data information further comprises data format information and data size information, and the mode information indicates a type of line buffer configuration.

18. The electronic system according claim 17, wherein the boundary generator generates the highest available address according to the data size information and the lowest available address.

19. The electronic system according to claim 17, wherein the boundary generator further generates a mid-point address for the line buffer configuration according to the highest available address.

20. The electronic system according to claim 16, wherein the memory is a Static Random Access Memory (SRAM) and is segmented into a higher half and a lower half.

21. The electronic system according to claim 20, wherein addresses of the higher half have ones as their most significant bits (MSBs), and addresses of the lower half have zeroes as their MSBs.

22. The electronic system according to claim 16, wherein the input data information comprises planar and packed video data.