Method apparatus, and system for efficient address and data protocol for a memory

• US 6,625,716 B2
• Filed: 06/28/2001
• Issued: 09/23/2003
• Est. Priority Date: 06/28/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fackenthal, Richard
• Primary Examiner(s): PORTKA, GARY J
• Application Number:
  US09/895,987
• Publication Number:
  US 20030028744A1
• Time in Patent Office: 817 Days
• Field of Search: 711/211, 711/1, 365/230.02, 365/233, 365/233.05, 365/230.01
• US Class Current: 711/211
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A memory to support an Address-Data Multiplexed protocol in response to a substantially simultaneous assertion of RAS and CAS, and an Address—Address Multiplexed protocol in response to an assertion of RAS followed by an assertion of CAS.

Claims

1. A system comprising:

at least one memory device, coupled to the system, to support an Address-Data Multiplexed protocol in response to a substantially simultaneous assertion of a Row Address Strobe (RAS) signal and a Column Address Strobe (CAS) signal and

to support an Address—

Address Multiplexed protocol in response to an assertion of RAS followed by an assertion of CAS.

2. The system of claim 1 wherein the Address-Data Multiplexed protocol allows the memory device to receive an address from a plurality of address pins and from a plurality of data pins in one clock cycle.

3. The system of claim 1 wherein the Address—

Address Multiplexed protocol allows the memory device to receive an address from a plurality of address pins in at least two clock cycles.

4. The system of claim 2 wherein the plurality of address pins is twelve and the plurality of data pins is sixteen.

5. The system of claim 3 wherein the plurality of address pins is twelve.

6. The system of claim 1 wherein the memory device is coupled to an embedded memory controller.

7. The system of claim 1 wherein the memory device is coupled to a memory controller.

8. The system of claim 1 wherein the memory device is coupled to a central processor unit.

9. The system of claim 1 wherein the memory device is coupled to a microcontroller.

10. The system of claim 1 wherein the memory device is a flash memory.

11. The system of claim 1 wherein the memory device is a flash memory embedded within the system.

12. The system of claim 1 wherein the memory device is a synchronous dynamic random access memory (SDRAM).

13. The system of claim 1 wherein the memory device is an embedded synchronous dynamic random access memory (SDRAM).

14. An apparatus comprising:

a memory controller; and

a memory, coupled to the memory controller, to multiplex between an Address-Data Multiplexed protocol and an Address—

Address Multiplexed protocol in response to either;

substantially simultaneous assertion of a Row Address Strobe (RAS) signal and a Column Address Strobe (CAS) signal;

or an assertion of RAS followed by an assertion of CAS.

15. The apparatus of claim 14 wherein the Address-Data Multiplexed protocol allows the memory to receive an address from a plurality of address pins and from a plurality of data pins in one clock cycle.

16. The apparatus of claim 14 wherein the Address-Address Multiplexed protocol allows the memory to receive an address from a plurality of address pins in at least two clock cycles.

17. The apparatus of claim 14 wherein the memory is a synchronous memory device.

18. The apparatus of claim 14 wherein the memory is a flash memory.

19. The apparatus of claim 14 wherein the memory device is an embedded flash memory.

20. The apparatus of claim 14 wherein the memory device is a synchronous dynamic random access memory (SDRAM).

21. The apparatus of claim 14 wherein the memory device is an embedded synchronous dynamic access random memory (SDRAM).

22. The apparatus of claim 15 wherein the plurality of address pins is twelve and the plurality of data pins is sixteen.

23. The apparatus of claim 16 wherein the plurality of address pins is twelve.

24. A method to communicate with a memory comprising:

sending a first address for an Address-Data Multiplexed protocol to the memory in response to a substantially simultaneous assertion of a Row Address Strobe (RAS) signal and a Column Address Strobe (CAS) signal; and

sending a second address for an Address—

Address Multiplexed protocol to the memory in response to an assertion of RAS followed by an assertion of CAS.

25. The method of claim 24 further comprising receiving at least one data bit from the memory for the Address-Data Multiplexed protocol and the Address—

Address Multiplexed protocol.

26. The method of claim 24 wherein the Address-Data Multiplexed protocol allows the memory to receive the first address from a plurality of address pins and from a plurality of data pins in one clock cycle.

27. The method of claim 24 wherein the Address—

Address Multiplexed protocol allows the memory to receive the second address from a plurality of address pins in at least two clock cycles.

28. The method of claim 24 wherein the memory is a flash memory.

29. The method of claim 24 wherein the memory is an embedded flash memory.

30. The method of claim 24 wherein the memory device is a synchronous dynamic random access memory (SDRAM).

31. The method of claim 24 wherein the memory device is an embedded synchronous dynamic random access memory (SDRAM).