Speculative reuse of code regions

• US 6,625,725 B1
• Filed: 12/22/1999
• Issued: 09/23/2003
• Est. Priority Date: 12/22/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fang, Jesse, Wu, Youfeng
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/470,113
• Time in Patent Office: 1,371 Days
• Field of Search: 712/216, 712/217, 712/205, 712/227, 712/200, 712/207, 712/245, 712/218, 712/248, 712/228, 711/133, 711/137, 703/22, 717/131, 717/140, 717/145, 717/146, 717/141, 717/165, 709/315, 709/314, 709/108
• US Class Current: 712/245
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3808 for instruction reuse, e.g. trace cache, branch target cache
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A speculative code reuse mechanism includes a reuse buffer, a main processing core and a reuse checking core. The reuse buffer includes inputs and outputs of previously executed instances of code reuse regions. Aliased reuse regions are regions that access memory locations that may change between executions of the region. When an aliased code reuse region is encountered and a matching instance exists in the reuse buffer, the main core speculatively executes code occurring after the reuse region, while the reuse checking core executes code from the reuse region to verify the matching instance. If the matching instance is verified, the speculative execution is committed, and if the matching instance is not verified, the speculative execution is squashed.

Claims

1. A processing apparatus comprising:

a first processor core configured to speculatively execute instructions based on results from an instance of a reuse region;

a second processor core configured to verify the results from the instance of the reuse region;

at least one queue coupled between the first processor core and the second processor core, wherein the at least one queue comprises a thread queue configured to hold at least one thread structure describing the reuse region and the instance of the reuse region.

2. A processing apparatus comprising:

a first processor core configured to speculatively execute instructions based on results from an instance of a reuse region;

a second processor core configured to verify the results from the instance of the reuse region;

a write-back buffer configured to hold results from speculatively executed instructions, and further configured to write back to the first processor core in response to verification of the results by the second processor core.

3. A processing apparatus comprising:

a first processor core configured to speculatively execute instructions based on results from an instance of a reuse region, wherein the reuse region includes an aliased load instruction that accesses an aliased memory address;

a second processor core configured to verify the results from the instance of the reuse region;

a reuse buffer configured to hold the instance of the reuse region; and

a reuse invalidation buffer configured to invalidate the instance of the reuse region in the reuse buffer responsive to a memory instruction that accesses the aliased memory address.

4. The processing apparatus of claim 3 wherein the reuse invalidation buffer includes:

a reference to the aliased memory address; and

a reuse instance index that points to the instance of the reuse region held in the reuse buffer.

5. A processing apparatus comprising:

a first processor core configured to speculatively execute instructions from a software region beyond a reuse region;

a thread queue coupled to the first processor core, the thread queue being configured to receive a thread structure describing the reuse region; and

a second processor core coupled to the thread queue, the second processor core being configured to execute instructions from the reuse region.

6. The processing apparatus of claim 5 wherein the thread structure describes an instance of the reuse region with information including:

reuse region instance input information; and

reuse region instance output information.

7. The processing apparatus of claim 6 further comprising a reuse invalidation buffer configured to include an aliased memory address accessed by an aliased load instruction within the reuse region.

8. The processing apparatus of claim 7 wherein the reuse invalidation buffer is further configured to include a pointer to the instance of the reuse region.

9. The processing apparatus of claim 6 wherein the second processor core is configured to execute the instructions from the reuse region, and to compare actual results to the reuse region instance output information.

10. The processing apparatus of claim 5 wherein the first processor core comprises a persistent register file and a shadow register file.

11. The processing apparatus of claim 10 wherein the second processor core comprises a local register file configured to receive information from the thread structure.

12. The processing apparatus of claim 5 further comprising a write-back buffer coupled to the first processor core, the write-back buffer being configured to store speculative results received from the first processor core.

13. The processing apparatus of claim 5 wherein the processing apparatus is a microprocessor.

14. A processing apparatus capable of speculative software execution, the apparatus comprising a checking processor core configured to execute software from a reuse region while a main processor core speculatively executes instructions occurring after the reuse region;

a reuse invalidation buffer having an entry that includes an aliased memory address and a pointer to a reuse region instance in a reuse buffer, such that the reuse region instance can be invalidated responsive to the entry;

a write-back buffer configured to hold speculative results from the speculative software execution.

15. A processing apparatus capable of speculative software execution, the apparatus comprising:

a main processor core;

a checking processor core configured to execute software from a reuse region while the main processor core speculatively executes instructions occurring after the reuse region, wherein the main processor core is configured to communicate reuse region information to the checking processor core in response to encountering a speculative reuse instruction;

a reuse invalidation buffer having an entry that includes an aliased memory address and a pointer to a reuse region instance in a reuse buffer, such that the reuse region instance can be invalidated responsive to the entry.

16. The processing apparatus of claim 15 further comprising a thread queue coupled between the main processor core and the checking processor core, the thread queue being configured to transfer the reuse region information from the main processor core to the checking processor core.

17. The processing apparatus of claim 16 wherein the thread queue is further configured to transfer reuse instance information including expected results to the checking processor core, and the checking processor core is further configured to compare the expected results with actual results.

18. A processing apparatus comprising:

a reuse buffer configured to hold a plurality of instances of reuse regions;

a reuse invalidation buffer configured to have a plurality of entries, each of the plurality of entries being configured to point to at least one of the plurality of instances of reuse regions held in the reuse buffer;

a processor core configured to search the reuse buffer for a matching instance when a reuse instruction is encountered, wherein

each of the plurality of entries in the reuse invalidation buffer is configured to include an aliased memory address,

each of the plurality of instances of reuse regions can be marked as valid or invalid within the reuse buffer, and

the processing core is configured to mark as invalid an instance of a reuse region pointed to by an entry in the reuse invalidation buffer when the corresponding aliased memory address is updated.

19. A computer-implemented method, comprising:

identifying a reuse region within a software program to be annotated;

determining whether the reuse region is aliased;

if the reuse region is aliased, adding a speculative reuse instruction to the reuse region;

if the reuse region is not aliased, adding a pure reuse instruction to the reuse region.

20. A computer-implemented method, comprising:

identifying a reuse region within a software program to be annotated;

determining whether the reuse region is aliased, comprising determining whether the reuse region includes a memory load instruction that accesses a memory location that is capable of being updated outside of the reuse region;

if the reuse region is aliased, adding a speculative reuse instruction to the reuse region.