Memory based phase locked loop

• US 6,625,765 B1
• Filed: 03/30/2000
• Issued: 09/23/2003
• Est. Priority Date: 03/31/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Krishnan, Rengarajan S.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Dooley, Matthew C.
• Application Number:
  US09/538,989
• Time in Patent Office: 1,272 Days
• Field of Search: 714/699, 714/740, 714/744, 714/718, 714/763, 331/25, 331/44, 324/76.82, 324/76.83, 327/5, 327/106, 327/156, 375/359, 375/371, 375/373, 375/375, 375/376
• US Class Current: 714/718
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.

Claims

1. A circuit comprising:

at least one column of memory cells;

a control circuit configured to read a sequence from the memory cells in a predetermined order and present a first output signal;

a sense amplifier configured to present a periodic signal in response to the first output signal and a first control signal; and

a phase detector/correction circuit configured to (i) receive a first reference signal and a first feedback of said periodic signal, and (ii) generate said first control signal.

2. The circuit according to claim 1, where said control circuit reads said sequence in response to said periodic signal, a second feedback of said periodic signal, or a second reference signal.

3. The circuit according to claim 1, wherein said first control signal provides phase correction by controlling a sense amplifier bias current.

4. The circuit according to claim 1, further comprising a second column of memory cells and a plurality of bitlines, and said control circuit comprises a multiplexer configured to present said first output signal from said plurality of bit lines.

5. The circuit according to claim 1, further comprising an array, wherein said array comprises:

a plurality of rows;

a first group of columns comprising said at least one column of memory cells; and

a second group of one or more columns, wherein one or more of the columns are written to in response to one or more second control signals, and wherein the number of columns enabled in said first group and said second group change a bitline swing presented to the sense amplifier.

6. The circuit according to claim 5, wherein said first control signal comprises an analog adjustment signal.

7. The circuit according to claim 6, wherein said phase detector/correction circuit is further configured to generate one or more digital adjustment signals.

8. The circuit according to claim 1, wherein said control circuit comprises a decoder.

9. The circuit according to claim 2, further comprising a second column of memory cells, and said control circuit comprises a multiplexer configured to select one of said columns in response to said periodic signal, said second feedback of said periodic signal or said second reference signal.

10. The circuit according to claim 6, wherein said phase detector/correction circuit comprises:

a phase detector receiving said first reference signal and said first feedback of said periodic signal, and presenting a digital adjustment signal; and

a phase error correction circuit configured to generate said analog adjustment signal.

11. The circuit according to claim 1, wherein said at least one column of memory cells each comprise static random access memory cells.

12. The circuit according to claim 2, wherein said phase detector/correction circuit comprises a counter.

13. A circuit comprising:

means for programming a series of memory cells with data defining a programmable frequency of a periodic signal;

means for sequentially reading the cells to generate an output signal; and

means for generating said programmable frequency from said output signal using circuitry comprising a sense amplifier.

14. A method for generating a signal having a programmable frequency comprising the steps of:

(A) programming a series of memory cells with data defining the frequency;

(B) reading the cells sequentially to generate an output signal; and

(C) generating the programmable frequency signal from the output signal using circuitry comprising a sense amplifier.

15. The method according to claim 14, where the cells are read sequentially in response to said programmable frequency signal, a feedback of said programmable frequency signal, or a reference signal.

16. The method according to claim 14, further comprising modifying a bit line swing at an input of the sense amplifier to change the frequency and/or a phase of the programmable frequency signal.

17. The method according to claim 14, wherein step (A) further comprises the substeps of:

(A-1) (i) enabling a first predetermined value of one or more first word lines of said series of memory cells or (ii) writing to said one or more first word lines said first predetermined value; and

(A-2) (i) enabling a second predetermined value of one or more second word lines of said series of memory cells or (ii) writing to said one or more second word lines said second predetermined value.

18. The circuit according to claim 14, wherein step (A) is responsive to one or more addresses.

19. The method according to claim 14, further comprising the step of:

(D) providing phase correction for said programmable frequency signal by adjusting a sense amplifier bias current.

20. The method according to claim 19, wherein step (D) is responsive to an analog adjustment signal.