Run-time controller in a functional verification system

• US 6,625,786 B2
• Filed: 12/14/2000
• Issued: 09/23/2003
• Est. Priority Date: 12/14/2000
• Status: Expired due to Term

• Current Assignee: Synopsys Emulation and Verification SA (Synopsys Incorporated)
• Original Assignee: Tharas Systems, Inc. (Synopsys Incorporated)
• Inventors: Broukhis, Leonid Alexander, Narayanaswamy, Ramesh, Nixon, Ian Michael, Ganesan, Subbu
• Primary Examiner(s): Garbowski, Leigh M.
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US09/738,272
• Publication Number:
  US 20020120907A1
• Time in Patent Office: 1,013 Days
• Field of Search: 716/1-21, 326/40, 365/201, 703/15, 714/30, 714/33, 714/728
• US Class Current: 716/106
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

Claims

1. A functional verification system performing the functional verification of a target design partitioned into a plurality of clusters, each of said clusters containing a plurality of combinatorial blocks, each of said plurality of clusters being uniquely identified by a cluster number, said plurality of clusters together representing said target design, said functional verification system comprising:

a plurality of combinatorial logic output evaluation units (CLOEs) being designed to evaluate said plurality of combinatorial blocks in each cluster in parallel; and

a run time controller sending a sequence of cluster numbers to said CLOEs, wherein each of said sequence of cluster numbers causes said plurality of CLOEs to evaluate combinatorial blocks contained in a corresponding one of said clusters,

whereby the sequence of evaluations can be controlled by appropriate partitioning of said target design and by sending cluster numbers in desired sequence.

2. The functional verification system of claim 1, wherein said run time controller receives a plurality of evaluation outputs from each of said plurality of CLOEs, wherein said evaluation outputs are generated by evaluating the corresponding combinatorial blocks.

3. The functional verification system of claim 2, wherein said run time controller determine a sequence of evaluation of said clusters by examining said plurality of evaluation outputs.

4. The functional verification system of claim 2, wherein said run time controller sends at least some of said plurality of evaluation outputs to all of said plurality of CLOEs.

5. The functional verification system of claim 4, wherein said run time controller comprises

a data unit receiving said plurality of evaluation outputs and sending at least some of said evaluation outputs on a bus, said data unit further injecting additional bits on said bus, wherein all of said plurality of CLOEs receive said evaluation outputs and said injected bits for future evaluations.

6. The functional verification system of claim 5, wherein said run time controller further comprises:

a simulation memory; and

a memory controller coupled to said simulation memory and said data unit, said memory controller providing data stored in said simulation memory to said data unit, wherein said provided data comprises said additional bits injected on said bus, whereby a memory read operation can be simulated by said functional verification system.

7. The functional verification system of claim 6, wherein said data unit provides some of said evaluation outputs to said memory controller for storing in said simulation memory such that a memory read operation can be simulated by said functional verification system.

8. The functional verification system of claim 5, further comprising a primary input memory coupled to said data unit, said primary input memory storing a primary input for said target design, said data unit providing said primary input as said additional bits such that said primary input can be used in evaluating combinatorial blocks.

9. The functional verification system of claim 5, further comprising a messaging unit sending data to said data unit, wherein said data unit provides data received from said messaging unit as said additional bits such that data can be provided from systems outside of said functional verification system to said CLOEs.

10. The functional verification system of claim 9, wherein said data unit sends said evaluation outputs to said messaging unit such that evaluation outputs can be sent to said systems outside of said functional verification system.

11. The functional verification system of claim 5, further comprising:

a flow control memory storing a plurality of flow control instructions, wherein each flow control instruction indicates a sequence of clusters to be evaluated; and

a flow processor coupled to said flow control memory and said CLOEs, said flow processor generating said sequence of cluster numbers according to said plurality of flow control instructions.

12. The functional verification system of claim 11, further comprising a cluster control memory coupled to said flow processor, said cluster control memory containing a cluster control memory location for each of said clusters wherein said flow processor accesses a cluster control memory location corresponding to a cluster which is evaluated.

13. The functional verification system of claim 12, wherein said data unit comprises an injection register, wherein said cluster control memory specifies when data is to be written into said injection register and when said data in said injection register is to be provided on said bus.

14. The functional verification system of claim 12, further comprises a plurality of registers, said flow control memory storing instructions which are designed to examine said registers and determine said sequence of cluster numbers based on the status of said registers, whereby said flow processor can execute loops until a desired condition is attained by.

15. The functional verification system of claim 14, wherein one of said registers comprises a counter, wherein said flow control memory stores instructions which are designed to modify the values in said counters.

16. The functional verification system of claim 14, wherein one of said registers comprises one or more condition bits, wherein said cluster control memory is designed to cause said flow processor to alter the status of said one or more condition bits based on said evaluation outputs received from said CLOEs.

17. The functional verification system of claim 13, wherein said cluster control memory specifies a specific cluster which generates an access address for a simulation memory, wherein said access address is contained in said evaluation outputs, and wherein said simulation memory is accessed based on said access address.

18. The functional verification system of claim 17, wherein said access comprises a read operation, and wherein said cluster control memory further specifies another cluster during the evaluation of which the data read from said simulation memory is to be stored in said injection register, said cluster control memory also specifying yet another cluster during the evaluation of which the data in said injection register is to be provided to said CLOEs.

19. The functional verification system of claim 17, wherein said access comprises a write operation, wherein said cluster control memory further specifies a specific cluster which generates the data to be written into said simulation memory, wherein said generated data is written into said simulation memory at said access address.

20. The functional verification system of claim 13, wherein said cluster control memory specifies a specific cluster during the evaluation of which a primary input to said target design is to be stored in said injection register and another specific cluster during the evaluation of which said primary input in said injection register is to be injected on said bus.

21. The functional verification system of claim 13, wherein said cluster control memory specifies a specific cluster during the evaluation of which data from a messaging unit is to be stored in said injection register and another specific cluster during the evaluation of which said data in said injection register is to be injected on said bus.

22. The functional verification system of claim 13, wherein said cluster control memory specifies a specific cluster during the evaluation of which said evaluation outputs are to be retrieved and provided to a messaging unit.

23. The functional verification system of claim 22, wherein said cluster control memory specifies a specific cluster during the evaluation of which data from a messaging unit is to be stored in said injection register and another specific cluster during the evaluation of which said data in said injection register is to be injected on said bus.