Semiconductor design system, semiconductor integrated circuit, semiconductor design method and storage medium storing semiconductor design program

• US 6,625,792 B1
• Filed: 07/20/2000
• Issued: 09/23/2003
• Est. Priority Date: 08/04/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Yamasaki, Kazuhito
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US09/620,471
• Time in Patent Office: 1,160 Days
• Field of Search: 716/8-14, 716/7
• US Class Current: 716/122
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/38 Circuit design at the mixed level of analogue and digital signals
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A semiconductor design system enhances layout on a semiconductor chip. Module layout positions of an integrated circuit chip are determined based on design information including information for connecting external circuits and modules information for connecting modules, macro information, and chip information. Before initiating detailed layout design of the chip, namely, in a stage where chip specifications are determined and before generation of an RTL description, accurate layout position information of modules are obtained. A determining unit determines a layout position of a module based on design information of information for connecting an external circuit to the module and information for interconnecting the module to other modules, macro information corresponding to a macro within the module and chip information corresponding to the semiconductor chip. A module moving unit moves the module having the associated macro to an area near a side of the semiconductor chip. The design information further has information about a size of the module, and the module layout position is determined by considering the size of the module.

Claims

1. A semiconductor design system to enhance layout on a semiconductor chip, comprising:

a determining unit determining a layout position of a module on a semiconductor chip before generation of an RTL description based on design information including information for connecting an external circuit to the module and information for interconnecting the module to other modules, macro information corresponding to a macro within the module and chip information corresponding to the semiconductor chip.

2. The semiconductor design system according to claim 1, further comprising:

a module moving unit moving the module having the associated macro to an area near a side of the semiconductor chip.

3. The semiconductor design system according to claim 1, wherein the design information further comprises information about a size of the module, and the module layout position is determined by considering the size of the module.

4. The semiconductor design system according to claim 1, wherein an input/output pad of the semiconductor chip is divided into a plurality of pad allocation areas.

5. The semiconductor design system according to claim 4, wherein the determining unit generates information of a terminal position for connecting modules.

6. The semiconductor design system according to claim 1, wherein other macros included in the module are allocated with a longest side length macro disposed toward a side of the semiconductor chip and remaining macros sequentially disposed toward chip center in order of macro length.

7. The semiconductor design system according to claim 6, wherein the chip is divided into four areas, with each area having an associated corner of the chip, and wherein the module having the longest sided macro among the modules in each area is allocated at a corresponding corner of the chip.

8. The semiconductor design system according to claim 6, wherein layout is determined so that a side of a macro included in the macro is disposed with signal terminals directed toward chip center.

9. The semiconductor design system according to claim 6, wherein the same type of macros within the module are disposed with signal terminals opposed to each other when arranged adjacently.

10. The semiconductor design system according to claim 6, wherein interval spacing between macros is adjusted considering the number of wiring layers, wiring direction of wiring layer or wiring interval of wiring layer.

11. The semiconductor design system according to claim 6, wherein the macro is moved to avoid overlap with fixed power supply wiring.

12. A semiconductor design system for designing before generation of an RTL description, comprising:

a module initial layout unit allocating a module to an initial predetermined position on a semicondutor chip;

a first module moving unit moving the module to an area closer to a pad allocating area of a plurality of pad allocation areas based on information for connecting an external circuit and the module;

a second module moving unit moving the module based on information of connecting the module with at least one of a plurality of other modules;

a third module moving unit moving modules having a macro to areas near a side of the chip;

a macro layout unit allocating macros to corresponding areas within each module; and

a macro moving unit moving a macro within each module to remove macro overlap.

13. The semiconductor design system according to claim 12, further comprising:

a first macro rotating unit rotating macros based on macro signal terminal positions.

14. The semiconductor design system according to claim 12, further comprising:

a second macro rotating unit rotating macros to use common signal lines among adjacent macros.

15. A semiconductor integrated circuit, comprising:

a plurality of grouped macros allocated with a longest side length macro disposed toward a side of a semiconductor chip and remaining macros sequentially disposed toward chip center in order of macro length.

16. The semiconductor integrated circuit according to claim 15, wherein the chip is divided into four areas, with each area having an associated corner of the chip, and wherein the module having the longest sided macro among the modules in each area is allocated at a corresponding corner of the chip.

17. The semiconductor integrated circuit according to claim 15, wherein layout is determined so that a side of a macro included in the module is disposed with signal terminals directed toward chip center.

18. The semiconductor integrated circuit according to claim 15, wherein the same type of macros within a module are disposed with signal terminals opposed to each other when arranged adjacently.

19. A storage medium storing a semiconductor design program to enhance layout on a semiconductor chip, comprising:

retrieving design information comprising information for connecting an external circuit to a module and information for interconnecting the module to other modules, macro information corresponding to a macro within the module and chip information corresponding to the semiconductor chip; and

determining a layout position of the module on the semiconductor chip based on the retrieved information.

20. The storage medium storing a semiconductor design program according to claim 19, further comprising:

allocating a module including macros in an area near a side of the chip.

21. The storage medium storing a semiconductor design program according to claim 19, wherein the design information includes information about module size, and wherein module layout position is determined considering the module size.

22. A method of designing layout on a semiconductor chip, comprising:

retrieving design information comprising information for connecting an external circuit to a module and information for interconnecting the module to other modules, macro information corresponding to a macro within the module and chip information corresponding to the semiconductor chip; and

determining a layout position of the module on the semiconductor chip based on the retrieved information.

23. A method of designing layout on a semiconductor chip before generation of an RTL description, comprising:

allocating a module to an initial predetermined position on a semiconductor chip;

moving the module to an area closer to a pad allocating area of a plurality of pad allocation areas based on information for connecting an external circuit and the module;

moving the module based on information of connecting the module with at least one of a plurality of other modules;

moving modules having a macro to areas near a side of the chip;

allocating macros to corresponding areas within each module; and

moving a macro within each module to remove macro overlap.

24. A semiconductor chip design system for determining layout of a plurality of modules on a semiconductor chip before generation of an RTL description, the chip having an input/output pad divided into a plurality of pad allocation areas and modules positioned on the chip at predetermined locations, the semiconductor chip design system comprising:

a module layout unit moving each of the modules on the chip based on design information for connecting each of the modules to corresponding pad allocation areas and other modules, and moving each module having one or more associated macros to a side of the chip; and

a macro layout unit positioning macros within the moved modules such that macros of each moved module do not overlap.

25. The semiconductor chip design system according to claim 24, wherein said macro layout unit arranges the macros within each moved module in a sequence according to the lengths of the macros, from longest to shortest, with the longest macro being positioned toward a side of the chip and the shortest macro being positioned toward the center of the chip.

26. The semiconductor chip design system according to claim 25, said module layout unit dividing the chip into four areas, each of the areas containing a corner of the chip, and arranging a module having the longest macro within each area near the corresponding corner of the chip.

27. The semiconductor chip design system of claim 24, wherein a macro within the moved modules has a side containing a plurality of signal terminals being positioned such that the side having the plurality of signal terminals is directed toward the center of the chip.

28. The semiconductor chip design system of claim 24, wherein a macro within the moved macros is moved when a fixed power supply wiring and the macro overlap.

29. A semiconductor chip design system, comprising:

a storage storing chip design information; and

a computer receiving the chip design information and moving each of modules on a chip based on the received chip design information, the chip design information instructing connecting each of the modules to corresponding pad allocation areas and other modules, moving each module having one or more associated macros to a side of the chip, and positioning the macros within the moved modules without overlapping macros of other modules.

30. The semiconductor chip design system according to claim 29, wherein said computer rotating the macros within the moved modules based on positions of signal terminals of the macros.

31. The semiconductor chip design system according to claim 29, wherein, when two adjacent macros within each moved module have the same type and the two adjacent macros have a side with a plurality of signal terminals, said computer positions the adjacent macros such that the sides of the macros having the plurality of signal terminals face one another.

32. The semiconductor chip design system of claim 29, wherein said computer rotates adjacent macros within the moved modules when the adjacent macros use a common signal.