Semiconductor device and method of manufacturing the same

• US 6,627,499 B2
• Filed: 11/27/2002
• Issued: 09/30/2003
• Est. Priority Date: 03/30/2000
• Status: Expired due to Term

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Osawa, Akihiko
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US10/305,197
• Publication Number:
  US 20030075760A1
• Time in Patent Office: 307 Days
• Field of Search: 438/138, 438/259, 438/268, 438/269, 438/270, 438/271, 438/272, 438/273, 438/274, 438/589, 438/612, 438/614, 257/76, 257/77, 257/327-334
• US Class Current: 438/259
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depletion layer is extended toward the base region so as to improve the breakdown voltage. The impurity diffusion region is formed by forming a trench in a part of the base region, a conductive film being buried in the trench, followed by introducing by ion implantation an impurity of the conductivity type equal to that in the base region into the side wall and the bottom of the trench in a concentration lower than that in the base region and subsequently diffusing the implanted impurity ions. The impurity diffusion region thus formed permits relaxing the electric field concentration on the corner portion of the gate trench and on the extended portion of the base region so as to improve the breakdown voltage.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor layer of a first conductivity type on one main surface of a semiconductor substrate;

forming a base region of a second conductivity type in a surface region of a drain region of the first conductivity type formed in the semiconductor layer of the first conductivity type;

forming a source region of the first conductivity type in a surface region of the base region;

forming a trench extending from the surface of the base region through the base region to reach an inner region of the drain region;

forming an impurity diffusion region of the second conductivity type having an impurity concentration lower than that in the base region in the periphery of the side wall of that portion of the trench which is positioned within the drain region;

burying a conductive layer and/or an insulating layer within the trench;

forming a gate insulating film in a manner to cover a part of the surfaces of the drain region, the base region and the source region; and

forming a gate electrode on the gate insulating film.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity diffusion region of the second conductivity type is formed by implanting ions of the impurity of the second conductivity type.

3. A method of manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor layer of a first conductivity type on one main surface of a semiconductor substrate;

forming a base region of a second conductivity type in a surface region of a drain region of the first conductivity type formed in the semiconductor layer of the first conductivity type;

forming a source region of the first conductivity type in a surface of the base region;

forming a first trench extending from the surface of the base region through the base region to reach an inner region of the drain region;

forming an impurity diffusion region of the second conductivity type having an impurity concentration lower than that in the base region in the periphery of the side wall of that portion of the first trench which is positioned within the drain region;

burying a conductive layer and/or an insulating layer within said first trench;

forming a second trench extending from the surface of the source region or from the surface of that portion of the base region which is contiguous to the source region to reach an inner region of the drain region;

forming a gate insulating film on the side wall and the bottom surface of said second trench; and

forming a gate electrode within the second trench in a manner to cover said gate insulating film.

4. The method of manufacturing a semiconductor device according to claim 3, wherein the depth of the first trench from the surface of the base region is larger than that of the second trench from the surface of the source region or from the surface of that portion of the base region which is contiguous to the source region.

5. The method of manufacturing a semiconductor device according to claim 4, wherein the impurity diffusion region of the second conductivity type is formed by ion implantation of an impurity of the second conductivity type.