Patterning three dimensional structures

• US 6,627,530 B2
• Filed: 12/22/2000
• Issued: 09/30/2003
• Est. Priority Date: 12/22/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek, Li, Calvin K., Knall, N. Johan, Vyvoda, Michael A.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): NGUYEN, KHIEM D
• Application Number:
  US09/746,204
• Publication Number:
  US 20020081833A1
• Time in Patent Office: 1,012 Days
• Field of Search: 438/622, 438/634, 438/40, 438/8, 438/9, 438/713, 438/618, 438/624
• US Class Current: 438/622
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal line, where the two signal lines comprise similar materials. The method includes selectively patterning the second signal line material and the circuit without patterning the first signal line. One way the second signal line is patterned without patterning the first signal line is by modifying the etch chemistry. A second way the second signal line is patterned without patterning the first signal line is by including an etch stop between the first signal line and the second signal line. The invention is also directed at targeting a desired edge angle of a stacked circuit structure. In terms of patterning techniques, a desired edge angle is targeted by modifying, for example, the etch chemistry from one that is generally anisotropic to one that has a horizontal component to achieve an edge angle that is slightly re-entrant (i.e., having negative slope).

Claims

1. A method comprising:

introducing at least a portion of a three dimensional circuit structure over a substrate in a stacked configuration between a first level of signal line material and a second level of signal line material, the first level of signal line material and the second level of signal line material comprising similar material; and

selectively patterning the second level of signal line material and at least part of the circuit structure, without patterning the first level of signal line material.

2. The method of claim 1 further comprising:

prior to patterning the second level of signal line material and the circuit structure, patterning the first level of signal line material into at least one signal line.

3. The method of claim 1, wherein patterning of the second level of signal line material and the circuit structure comprises etching the second level of signal line material with an etch chemistry that selectively favors etching of the second level of signal line material over the first level of signal line.

4. The method of claim 3, wherein etching comprises sequentially etching with a first etch chemistry favoring etching of the second level of signal line material and a second different etch chemistry disfavoring the etching of the second level of signal line material.

5. The method of claim 4, wherein the first etch chemistry comprises a first chemistry resulting in a generally anisotropic feature definition and a second chemistry resulting in etching with a horizontal component.

6. The method of claim 5, wherein selectively patterning the second signal line material and the circuit structure comprises:

cumulatively patterning the second signal line material and the circuit structure with the first chemistry and second chemistry such that,

a sum of the first chemistry and the second chemistry patterning yields an edge of a patterned circuit structure with an edge angle between about 85° and

about 90°

relative to a surface of the first signal line material.

7. The method of claim 5, further comprising:

prior to patterning the second signal line material, introducing a photoimageable mask material over a hard mask material, the photoimageable mask material defining an etch pattern;

patterning at least the hard mask material through the photoimageable mask material;

removing the photoimageable mask material; and

patterning the circuit device portion through the hard mask material.

8. The method of claim 2, wherein each of the first and the second level of signal line material comprises at least a first phase and a second phase.

9. The method of claim 8 wherein each of the first and the second levels of signal line material is introduced as a first phase material.

10. The method of claim 8, wherein the first signal line material and the second signal line material is a refractory metal silicide.

11. The method of claim 8, further comprising prior to patterning the second signal line material, transforming the first level of signal line material to a second phase.

12. The method of claim 9, wherein the introduction of the three dimensional circuit structure comprises introducing an etch stop immediately above the first signal line material.

13. The method of claim 12, wherein a portion of the circuit structure comprises the etch stop.

14. The method of claim 1 further comprising:

prior to selectively patterning the second level of signal line material, introducing a second portion of the three-dimensional circuit structure over the second level of signal line material.

15. A method comprising:

introducing a first three dimensional circuit portion over a first signal line material;

patterning the first signal line material into a first signal line;

introducing a second signal line material similar to the first signal line material over the first three dimensional circuit portion; and

patterning the second signal line material into a second signal line and the three dimensional circuit, the patterning stopping prior to exposing the first signal line.

16. The method of claim 15, wherein patterning of the second signal line material comprises etching the second signal line material with an etch chemistry that selectively favors etching of the second signal line material over the first signal line material.

17. The method of claim 15, wherein introducing the three dimensional circuit comprises introducing an etch stop material between the first three dimensional circuit portion and the first signal line material and patterning comprises stopping at the etch stop.

18. The method of claim 17, wherein the etch stop comprises a portion of the three dimensional circuit.

19. The method of claim 15, further comprising patterning the second signal line material generally orthogonal to the at least one first signal line.

20. The method of claim 15, wherein patterning comprises sequentially etching with a first etch chemistry favoring etching of the second signal line material and a second etch chemistry disfavoring the etching of the second signal line material.

21. The method of claim 20, wherein the first etch chemistry comprises a first chemistry providing a generally anisotropic feature definition and a second chemistry including a horizontal etching component, the method further comprising:

patterning the second signal line material with the first chemistry; and

patterning a portion of the circuit device with the second chemistry,

wherein the sum of the first chemistry and the second chemistry patterning yields an edge of the patterned circuit device with an edge angle between about 85° and

about 90°

measured from the first signal line material.

22. The method of claim 15, further comprising:

prior to patterning the second signal line material, introducing a photoimageable mask material over a hard mask material, the photoimageable mask material defining the etch pattern;

patterning at least the hard mask through the photoimageable mask material;

removing the photoimageable mask material; and

patterning the circuit device through the hard mask material.

23. The method of claim 15, wherein each of the first signal line material and the second signal line material has at least a first phase and a second phase and each of the first signal line material and the second signal line material is introduced substantially as the first phase.

24. The method of claim 23, wherein the material for each of the signal line material and the second signal line material is a refractory metal silicide.

25. The method of claim 24, wherein an oxide layer is formed directly over the first signal line material.

26. The method of claim 23, wherein introducing the first three dimensional circuit portion comprises introducing an etch stop directly over the first signal line material, the method further comprising prior to patterning the second signal line material, transforming the first signal line material to the second phase.

27. The method of claim 15 further comprising:

prior to patterning the second signal line material, introducing a second three dimensional circuit portion over the second signal line material.

28. A method comprising:

introducing a three dimensional circuit portion over a first signal line material on a substrate; and

patterning the three dimensional circuit portion and the first signal line material into strips,

wherein the strips have a re-entrant profile.

29. The method of claim 28, wherein patterning the three dimensional circuit portion and the first signal line material into strips comprises sequentially patterning with two different etch chemistries.

30. The method of claim 29, wherein a first etch chemistry is vertically anisotropic and a second etch chemistry includes a horizontal component.