Self-aligned floating gate poly for a flash E2PROM cell

• US 6,627,942 B2
• Filed: 07/26/2001
• Issued: 09/30/2003
• Est. Priority Date: 03/29/2001
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Wang, Chih Hsin
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/916,423
• Publication Number:
  US 20020142544A1
• Time in Patent Office: 796 Days
• Field of Search: 438/435, 438/437, 438/221, 438/296, 757/314-317
• US Class Current: 257/315
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Method and apparatus for isolating active regions in an electrically programmable and erasable memory device. A first layer of insulating material is formed on a substrate. A layer of conductive material is formed on the first layer of insulating material. A plurality of spaced apart trenches are formed through the first layer of insulating material, the layer of conductive material, and into the substrate. A second layer of insulation material is formed on sidewall portions of the trenches. A block of insulation material is formed in the trenches. For each of the trenches, an edge portion of the layer of conductive material extends over and overlaps with the first layer of insulating material and possibly a portion of the insulation material block by a predetermined distance Δ. For each of the trenches, the predetermined distance Δ is selected so that after back end processing is performed to the substrate and the conductive layer, the edge portion of the conductive layer is aligned to the sidewall portion of the isolation trench.

Claims

1. A semiconductor structure for use in the manufacture of an electrically programmable and erasable memory device, comprising:

a substrate of semiconductor material of a first conductivity type;

a first layer of insulating material formed on the substrate;

a layer of conductive material formed on the first layer of insulating material;

a plurality of spaced apart trenches extending through the first layer of insulating material, the layer of conductive material, and into the substrate;

a second layer of insulation material formed on sidewall portions of the trenches; and

a block of insulation material formed in the trenches;

wherein for each of the trenches, an edge portion of the layer of conductive material extends over and overlaps with the second layer of insulating material by a predetermined distance Δ

; and

wherein for each of the trenches, the edge portion of the layer of conductive material further extends over and overlaps with a portion of the block of insulation material.

2. A semiconductor structure for use in the manufacture of an electrically programmable and erasable memory device, comprising:

a substrate of semiconductor material of a first conductivity type;

a first layer of insulating material formed on the substrate;

a layer of conductive material formed on the first layer of insulating material;

a plurality of spaced apart trenches extending through the first layer of insulating material, the layer of conductive material, and into the substrate;

a second layer of insulation material formed on sidewall portions of the trenches; and

a block of insulation material formed in the trenches;

wherein for each of the trenches, an edge portion of the layer of conductive material extends over and overlaps with the second layer of insulating material by a predetermined distance Δ

; and

wherein for each of the trenches, the predetermined distance Δ

is selected so that after back end processing is performed to the substrate and the conductive layer, the edge portion is substantially aligned to the sidewall portion of the trench.