Integrated low ripple, high frequency power efficient hysteretic controller for dc-dc converters

• US 6,628,109 B2
• Filed: 06/18/2001
• Issued: 09/30/2003
• Est. Priority Date: 06/26/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rincon-Mora, Gabriel A.
• Primary Examiner(s): Berhane, Adolf D.
• Application Number:
  US09/883,780
• Publication Number:
  US 20010054883A1
• Time in Patent Office: 834 Days
• Field of Search: 323/280, 323/282, 323/284, 323/351
• US Class Current: 323/282
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence

Abstract

The present invention relates to a method of improving power efficiency in a converter circuit at low load currents. The method comprises the steps of monitoring a load current of the converter circuit and adjusting a natural frequency of the converter circuit based on the load current. Such an adjustment of the natural frequency results in a reduction in switching losses at low load currents, thereby improving the power efficiency associated therewith. The present invention also relates to a circuit for improving a power efficiency in a dc—dc converter. The circuit comprises a converter circuit and a comparator circuit coupled to an input of the converter circuit. The dc—dc converter also comprises a feedback circuit coupled between an input and an output of the comparator circuit; the feedback circuit is operable to alter a trip frequency of the comparator circuit as a function of a load current at an output of the converter circuit, thereby decreasing switching losses at low load currents and improving the power efficiency associated therewith.

Claims

1. A method of improving power efficiency in a hysteretic DC—

DC converter circuit at low load currents, comprising the steps of;

monitoring a load current of the converter circuit; and

adjusting a natural frequency of the converter circuit based on the load current.

2. The method of claim 1, wherein adjusting the natural frequency comprises making the natural frequency a generally linear function of the load current.

3. The method of claim 1, wherein adjusting the natural frequency comprises making the natural frequency a discrete function of the load current.

4. The method of claim 1, wherein adjusting the natural frequency comprises decreasing the natural frequency of the converter circuit when the load current decreases.

5. The method of claim 1, wherein monitoring the load current comprises detecting a voltage across a resistor having the load current conducting therethrough or a current associated with the load current conducting therethrough.

6. A method of improving power efficiency in a converter circuit at low load currents, wherein the converter circuit comprises a buck converter circuit having an input terminal and an output terminal which forms a converter circuit output, and a comparator circuit having an output coupled to the input terminal of the buck converter circuit, a first input coupled to the converter circuit output, and a second input coupled to an input reference voltage, comprising the steps of:

monitoring a load current of the converter circuit; and

adjusting a natural frequency of the converter circuit based on the load current by

generating a ramp voltage signal having a ramp rate associated therewith which is a function of the load current, and

using the ramp voltage signal to alter a trip frequency of the comparator circuit, wherein the trip frequency is related to the natural frequency of the converter circuit.

7. The method of claim 6, wherein the ramp voltage signal contains duty cycle information associated with the buck converter circuit.

8. The method of claim 6, wherein using the ramp voltage signal to alter the trip frequency comprises superimposing the ramp voltage signal on the reference voltage.

9. The method of claim 8, further comprising modulating the ramp rate of the ramp voltage signal in a manner which is related to the load current.

10. The method of claim 9, wherein the ramp rate is modulated by a signal which is proportional to the load current.

11. The method of claim 8, wherein generating the ramp voltage comprises generating a charge current and a discharge current for charging and discharging a capacitor, respectively, wherein one or both of the charge current and the discharge current are a function of the load current.

12. The method of claim 11, wherein generating the charge current comprises:

generating a reference current; and

adding a correction current to the reference current, wherein the correction current has a magnitude which is a function of the load current, and wherein the reference current and the correction current together form the charge current.

13. The method of claim 12, wherein generating the correction current comprises:

generating a differential input voltage which is a function of the load current; and

placing the differential input voltage across inputs terminals of a differential transconductor amplifier, wherein an output current of the differential transconductor amplifier is a function of the differential input voltage and thus a function of the load current.

14. A circuit for improving a power efficiency in a hysteretic DC—

DC converter, comprising;

a converter circuit;

a comparator circuit coupled to an input of the converter circuit; and

a feedback circuit coupled between an input and an output of the comparator circuit, wherein the feedback circuit is operable to alter a trip frequency of the comparator circuit as a function of a load current at an output of the converter circuit.

15. The circuit of claim 14, wherein the converter circuit comprises a buck converter circuit.

16. The circuit of claim 14, wherein an output of the converter circuit is fed back to an input of the comparator circuit, and wherein the comparator inputs from the converter circuit output and the feedback circuit dictate the trip frequency of the comparator circuit.

17. The circuit of claim 14, wherein the feedback circuit further comprises an output load current sense circuit, and wherein the feedback circuit generates a ramp signal that is fed to an input of the comparator circuit which is a function of the load current.

18. The circuit of claim 17, wherein the ramp signal has a slope which is a function of the load current.

19. The circuit of claim 18, wherein the slope of the ramp signal decreases as the load current decreases, and wherein a decrease in the slope of the ramp signal decreases the trip frequency of the comparator circuit, thereby decreasing the natural frequency of the dc—

dc converter at low load currents.

20. A circuit for improving a power efficiency across a range of load currents in a dc—

dc converter, comprising;

a buck converter circuit having an input and an output, wherein the output of the buck converter circuit comprises an output of the dc—

dc converter;

a comparator circuit having a first input, a second input and an output, wherein the output is coupled to the input of the buck converter circuit, and the output of the buck converter is coupled to the first input of the comparator circuit; and

a feedback circuit having an input coupled to the output of the comparator circuit and an output coupled to the second input of the comparator circuit, which is also coupled to an input reference voltage,

wherein the feedback circuit is operable to provide a feedback signal which is superimposed over the input reference voltage, and wherein the feedback signal is a function of a load current of the dc—

dc converter, and further wherein the feedback signal is operable to alter a trip frequency of the comparator circuit, thereby impacting a natural frequency of the dc—

dc converter as a function of the load current.

21. The circuit of claim 20, wherein the feedback circuit via the feedback signal is operable to decrease the trip frequency of the comparator circuit as the load current decreases, thereby reducing a switching loss associated with the dc—

dc converter at low load currents and improving power efficiency.

22. The circuit of claim 20, wherein the feedback signal comprises a ramp signal having a slope which is a function of the load current, and wherein the slope of the ramp signal dictates the trip frequency of the comparator circuit, thereby altering the natural frequency of the dc—

dc converter.

23. The circuit of claim 22, wherein the slope of the ramp signal decreases as the load current decreases.

24. The circuit of claim 22, wherein the feedback circuit comprises:

a positive ramp circuit operable to dictate a positive slope of the ramp signal;

a negative ramp circuit operable to dictate a negative slope of the ramp signal; and

a ramp capacitor which charges at a rate dictated by the positive ramp circuit and discharges at a rate dictated by the negative ramp circuit, and wherein the ramp signal is related to a voltage across the ramp circuit.

25. The circuit of claim 24, wherein the positive ramp circuit comprises a positive ramp current source and a switch, wherein the switch is operable to couple the positive ramp current source to the ramp capacitor for charging thereof based on a state of the output of the comparator circuit, and wherein the positive ramp current source charges the ramp capacitor with a current which is a function of the load current.

26. The circuit of claim 25, wherein the charging current of the positive ramp current source decreases as the load current decreases, thereby decreasing a rate at which the ramp capacitor charges, which decreases the slope of the ramp signal and decreases the trip frequency of the comparator circuit.

27. The circuit of claim 25, wherein the positive ramp current source comprises:

a transconductance amplifier having a differential input; and

a sense resistor coupled across the differential input having a current conducting therethrough which is associated with the load current, thereby causing a differential input voltage to develop across the differential input which is associated with the load current,

wherein the transconductance amplifier is operable to generate a current which is a function of the differential input voltage and thus a function of the load current.

28. The circuit of claim 24, wherein the negative ramp circuit comprises a negative ramp current source and a switch, wherein the switch is operable to couple the negative ramp current source to the ramp capacitor for discharging thereof based on a state of the output of the comparator circuit, and wherein the negative ramp current source discharges the ramp capacitor with a current which is a function of the load current.

29. The circuit of claim 28, wherein the discharging current of the negative ramp current source decreases as the load current decreases, thereby decreasing a rate at which the ramp capacitor discharges, which decreases the slope of the ramp signal and decreases the trip frequency of the comparator circuit.

30. The circuit of claim 28, wherein the negative ramp current source comprises:

a transconductance amplifier having a differential input; and

a sense resistor coupled across the differential input having a current conducting therethrough which is associated with the load current, thereby causing a differential input voltage to develop across the differential input which is associated with the load current,

wherein the transconductance amplifier is operable to generate a current which is a function of the differential input voltage and thus a function of the load current.