Circuit for tuning an active filter

• US 6,628,163 B2
• Filed: 06/27/2002
• Issued: 09/30/2003
• Est. Priority Date: 11/15/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Drescher, Henry, Dathe, Lutz
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US10/185,146
• Publication Number:
  US 20030090316A1
• Time in Patent Office: 460 Days
• Field of Search: 327/551, 327/552, 327/553, 327/554, 327/558, 327/559
• US Class Current: 327/553
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank

Abstract

A circuit comprises an active filter with linear elements and a tuning circuit with linear elements of the same type as the filter circuit. A backward counter generates a count value that represents a time constant of the tuning circuit. The initial value of the backward counter contains information concerning the relationship between the time constant of the filter circuit and the tuning circuit. A decoder creates a digital code responsive to the count value which is used to switch an array of linear elements in order to tune the time constant of the filter to approximately a desired design value.

Claims

1. A circuit including

an active filter having a plurality of first linear electronic elements arranged as a switchable array and at least one second linear electronic element, the first linear electronic elements having an electrical characteristic represented by a first design value and the second linear electronic element having an electrical characteristic represented by a second design value, the first and second linear electronic elements substantially determining a time constant of the active filter, and

a tuning circuit for outputting a digital code n to the array of first linear electronic elements to adjust the time constant of the active filter approximately to a predefined value, the tuning circuit comprising:

a first linear tuning element having an electrical characteristic represented by the first design value times a first predefined factor K_C;

a second linear tuning element having an electrical characteristic represented by the second design value times a second predefined factor K_R;

a signal generator configured to generate a signal indicative of a tuning time constant determined by the first and second linear tuning elements;

a backward counter having

a reset input configured to reset the backward counter upon receipt of a reset signal to an initial value x_max that includes a relationship of the time constant of the active filter circuit and the tuning time constant;

a clock input connected to receive a clock signal,

an enable input connected to the signal generator to receive a signal for starting the counter with the initial value x_max and stopping the counter in order to generate a count value x_n, and

a counter output configured to provide the count value x_n; and

a decoder configured to convert the count value x_n into a digital code n for switching the array of first linear electronic elements.

2. The circuit of claim 1, wherein the relationship of the time constant of the active filter circuit and the tuning time constant is substantially proportional to K_C and K_R.

3. The circuit of claim 1, wherein the digital code output by the decoder is determined on the basis of a ratio x_n/(x_max−

x_n).

4. The circuit of claim 1, wherein the first linear electronic elements are capacitors.

5. The circuit of claim 1, wherein the second linear electronic element is one of an inductor and a resistor.

6. The circuit of claim 1, wherein a predefined number of the first linear electronic elements are connected to represent the first design value.

7. The circuit of claim 1, further comprising one or more first linear electronic elements that are permanently connected.

8. The circuit of claim 1, wherein the decoder comprises a memory including a look-up table for storing different values of the digital code n.

9. The circuit of claim 8, wherein the values for the digital code n stored in the look-up table are calculated using the equation n=x_n n₀/(x_max−

x_n), wherein n₀ is the number of permanently connected first linear electronic elements in the switchable array.

10. The circuit of claim 9, wherein the values for the digital code n are obtained as integer numbers by using one of the round and clipping function.

11. The circuit of claim 1, wherein the first and second predefined factors are integer values.

12. The circuit of claim 1, further comprising a latch for storing the digital code n.

13. The circuit of claim 1, further comprising a power controller to power down the tuning circuit after creating the digital code n.

14. The circuit of claim 1, wherein the circuit is an integrated circuit.

15. The circuit of claim 1, further comprising a switching means for connecting at least one of the first linear electronic elements and the second linear electronic element as the first and second linear tuning elements, respectively, to the decoder.

16. The circuit of claim 1, wherein said signal comprises two subsequent pulses the rising edges of which define an interval indicative of said tuning time constant.

17. The circuit of claim 16, wherein said interval is substantially equal to the tuning time constant.

18. The circuit of claim 1, wherein said signal comprises a pulse whose pulse length is indicative of the tuning time constant.

19. A circuit including

an active filter having a plurality of first linear electronic elements at least some of which are arranged as a switchable array and a second linear electronic element, each of the first linear electronic elements corresponding to a first design value and the second linear electronic element corresponding to a second design value, the first and second linear electronic elements substantially determining a time constant of the active filter,

a first linear tuning element having an electrical characteristic determined by the first design value;

a second linear tuning element having an electrical characteristic determined by the second design value;

the first and second tuning element defining a tuning time constant;

means for generating a signal indicative of the tuning time constant;

means for providing an output count value on the basis of an initial count value representing a relationship between the time constant and the tuning time constant; and

means for providing a digital code to the switchable array on the basis of the output count value in order to adjust the time constant.

20. The circuit of claim 19, wherein the electrical characteristic of the first linear tuning element is substantially proportional to the first design value.

21. The circuit of claim 19, wherein the electrical characteristic of the second linear tuning element is substantially proportional to the second design value.

22. The circuit of claim 19, wherein the signal comprises two subsequent pulses the rising edges of which define an interval indicative of said tuning time constant.

23. A method of tuning an active filter, the active filter comprising a plurality of first linear electronic elements at least some of which are arranged as a switchable array, and a second linear electronic element, each of the first linear electronic elements corresponding to a first design value and the second linear electronic element corresponding to a second design value, the first and second linear electronic elements substantially determining a time constant of the active filter, the method comprising:

generating a signal indicative of a tuning time constant defined by a first linear tuning element and a second linear tuning element, wherein an electrical characteristic of the first linear tuning element is determined by the first design value, and an electrical characteristic of the second linear tuning element is determined by the second design value;

starting and stopping, on the basis of said signal, a counter operated at a clock frequency to generate a count value, wherein an initial count value of the counter is determined by the time constant and the tuning time constant.

24. The method of claim 23, wherein generating said signal includes producing two subsequent pulse signals defining a time interval that determines the tuning time constant.

25. The method of claim 24, wherein said time interval is determined by rising edges of said two subsequent pulse signals.

26. The method of claim 23, wherein said initial count value is proportional to the first design value, the second design value, the clock frequency and a predefined maximum variation of the time constant.

27. The method of claim 23, further comprising converting said count value in a digital code, and providing the digital code to means for selectively connecting one or more of the first linear electronic elements to readjust the time constant.

28. The method of claim 27, wherein said digital code is provided as an integer number.

29. The method of claim 27, wherein values of said digital code are stored in advance in a memory.

30. The method of claim 28, wherein said digital code is computed by using one of a round function and a clipping function.