Presenting independent images on multiple display devices from one set of control signals

• US 6,628,243 B1
• Filed: 12/09/1999
• Issued: 09/30/2003
• Est. Priority Date: 12/09/1999
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Low, William, Lyons, George
• Primary Examiner(s): Shankar, Vijay
• Assistant Examiner(s): Said, Mansour M.
• Application Number:
  US09/458,263
• Time in Patent Office: 1,391 Days
• Field of Search: 345/1.1, 345/1.2, 345/1.3, 345/3.1, 345/3.2, 345/208, 345/209, 345/210, 345/211, 345/212, 345/213, 345/214, 345/1, 345/9, 345/87, 345/90, 345/98, 345/99, 345/100, 345/204
• US Class Current: 345/1.1
• CPC Class Codes: G06F 3/1431 using a single graphics controller
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

Multiple independent images are presented on multiple display devices by driving the display devices with a common set of control signals and a multiplexed set of data signals that convey information representing interleaved components of each independent image. In a preferred embodiment, a unique clock signal is provided to each respective display device that is aligned with the interleaved components of the image to be presented by that respective display. The control, data and clock signals may be obtained by multiplexing control and data signals received from display pipeline circuits, or by generating the, signals using a composite circuit that implements the features of two or more multiplexed display pipeline circuits.

Claims

1. An apparatus comprising:

input-interface circuitry that receives data signals representing a plurality of independent images and associated control signals;

memory;

memory controller in communication with the input-interface circuitry and the memory to control writing information into and reading information from the memory, wherein the information corresponds to the data signals representing the plurality of independent images;

one or more display-pipeline circuits in communication with the memory to receive the information representing the plurality of independent images; and

output terminals in communication with the one or more display-pipeline circuits, wherein the output terminals provide a first clock signal and a plurality of output-data signals conveying interleaved components of the plurality of independent images, wherein each component represents a portion of a respective image that is narrower than the respective image, and wherein the output-data signals conveying components for a first of the plurality of independent images are aligned with the first clock signal.

2. An apparatus according to claim 1 that generates a second clock signal, wherein the output-data signals conveying components for a second of the plurality of independent images are aligned with the second clock signal.

3. An apparatus according to claim 2 that generates output-data signals along a plurality of data-signal paths, generates the first clock signal along a first clock-signal path and generates the second clock signal along a second clock-signal path.

4. An apparatus according to claim 1 that generates output-data signals along a plurality of data-signal paths, and generates the first clock signal along a first clock-signal path.

5. An apparatus according to claim 1 wherein a respective component represents a pixel of a respective one of the plurality of independent images.

6. An apparatus according to claim 1 that generates a third clock signal and the output-data signals conveying components for a third of the plurality of independent images are aligned with the third clock signal.

7. An apparatus according to claim 1 that comprises only one display-pipeline circuit.

8. An apparatus according to claim 7 wherein the display-pipeline circuit comprises only one first-in-first-out buffer circuit in communication with the memory to receive signals conveying interleaved components of the plurality of independent images.

9. An apparatus according to claim 7 wherein the display-pipeline circuit comprises only one lookup-table circuit in communication with the memory to receive signals conveying interleaved components of the plurality of independent images.

10. An apparatus according to claim 1 that comprises more than one display-pipeline circuit and a multiplexing circuit in communication with the display-pipeline circuits, wherein the multiplexing circuit interleaves signals received from the display-pipeline circuits that represent components of the independent images.

11. An apparatus according to claim 10 wherein each display-pipeline circuit comprises a respective first-in-first-out buffer circuit.

12. A system comprising:

processor circuitry that generates data signals representing a plurality of independent images and associated control signals;

input-interface circuitry in communication with the processor circuitry to receive the data signals and the associated control signals;

memory;

memory controller in communication with the input-interface circuitry and the memory to control writing information into and reading information from the memory, wherein the information corresponds to the data signals representing the plurality of independent images;

one or more display-pipeline circuits in communication with the memory to receive the information representing the plurality of independent images;

output terminals in communication with the one or more display-pipeline circuits, wherein the output terminals provide a first clock signal and a plurality of output-data signals conveying interleaved components of the plurality of independent images, wherein each component represents a portion of a respective image that is narrower than the respective image, and wherein the output-data signals conveying components for a first of the plurality of independent images are aligned with the first clock signal; and

a plurality of display devices in communication with the output terminals, wherein a respective display device presents a respective one of the plurality of independent images.

13. A system according to claim 12 that generates a second clock signal, wherein the output-data signals conveying components for a second of the plurality of independent images are aligned with the second clock signal.

14. A system according to claim 13 that generates output-data signals along a plurality of data-signal paths, generates the first clock signal along a first clock-signal path and generates the second clock signal along a second clock-signal path.

15. A system according to claim 12 that generates output-data signals along a plurality of data-signal paths, and generates the first clock signal along a first clock-signal path.

16. A system according to claim 12 wherein a respective component represents a pixel of a respective one of the plurality of independent images.

17. A system according to claim 12 that generates a third clock signal and the output-data signals conveying components for a third of the plurality of independent images are aligned with the third clock signal.

18. A system according to claim 12 that comprises only one display-pipeline circuit.

19. A system according to claim 18 wherein the display-pipeline circuit comprises only one first-in-first-out buffer circuit in communication with the memory to receive signals conveying interleaved components of the plurality of independent images.

20. A system according to claim 18 wherein the display-pipeline circuit comprises only one lookup-table circuit in communication with the memory to receive signals conveying interleaved components of the plurality of independent images.

21. A system according to claim 12 that comprises more than one display-pipeline circuit and a multiplexing circuit in communication with the display-pipeline circuits, wherein the multiplexing circuit interleaves signals received from the display-pipeline circuits that represent components of the independent images.

22. A system according to claim 21 wherein each display-pipeline circuit comprises a respective first-in-first-out buffer circuit.

23. A method for transmitting signals representing two or more independent images for presentation by two or more display devices, the method comprising:

generating a sequence of first signal components representing components of a first image, wherein a respective first signal component represents a respective component of the first image that is narrower than the first image;

generating a sequence of second signal components representing components of a second image that is independent of the first image, wherein a respective second signal component represents a respective component of the second image that is narrower than the second image; and

transmitting along a data-signal channel the first signal components interleaved with the second signal components and transmitting along a control-signal channel a first clock signal, wherein a respective first signal component is aligned with a respective cycle of the first clock signal.

24. A method according to claim 23 wherein a respective second signal component is aligned with a respective cycle of a second clock signal.

25. A method according to claim 24 wherein the second clock signal is inverted with respect to the first clock signal.

26. A method according to claim 23 wherein a respective first signal component is transmitted along the data-signal channel by generating digital signals along a plurality of data-signal paths, a respective second signal component is transmitted along the data-signal channel by generating digital signals along the plurality of data-signal paths, and the first clock signal is transmitted along the control-signal channel by generating a digital signal along a first clock-signal path.

27. A method according to claim 26 that transmits

a vertical-synchronization signal along a vertical-synchronization-signal path, and

a horizontal-synchronization signal along a horizontal-synchronication-signal path; and

wherein

the data-signal channel comprises two or more data-signal paths,

the control-signal channel comprises the first clock-signal path, the vertical-synchronization-signal path, and the horizontal-synchronication-signal path, and

the data-signal channel and the control-signal channel convey signals that are compatible with a liquid crystal display panel.

28. A method according to claim 23 wherein a respective first signal component represents a respective pixel of the first image and a respective second signal component represents a respective pixel of the second image.

29. A method according to claim 23 that comprises:

generating a sequence of third signal components representing components of a third image that is independent of the first and second images, wherein a respective third signal component represents a respective component of the third image that is narrower than the third image; and

transmitting along the data-signal channel the third signal components interleaved with the first and second signal components.

30. A method according to claim 29 that comprises transmitting along the control-signal channel a second clock signal and a third clock signal, wherein a respective second signal component is aligned with a respective cycle of the second clock signal and a respective third signal component is aligned with a respective cycle of the third clock signal.

31. An apparatus for transmitting signals representing two or more independent images for presentation by two or more display devices, the apparatus comprising:

means for generating a sequence of first signal components representing components of a first image, wherein a respective first signal component represents a respective component of the first image that is narrower than the first image;

means for generating a sequence of second signal components representing components of a second image that is independent of the first image, wherein a respective second signal component represents a respective component of the second image that is narrower than the second image; and

means for transmitting along a data-signal channel the first signal components interleaved with the second signal components and transmitting along a control-signal channel a first clock signal, wherein a respective first signal component is aligned with a respective cycle of the first clock signal.

32. An apparatus according to claim 31 wherein a respective second signal component is aligned with a respective cycle of a second clock signal.

33. An apparatus according to claim 31 wherein the second clock signal is inverted with respect to the first clock signal.

34. An apparatus according to claim 31 that comprises:

means for generating digital signals along a plurality of data-signal paths to transmit a respective first signal component along the data-signal channel;

means for generating digital signals along the plurality of data-signal paths to transmit a respective second signal component along the data-signal channel; and

means for generating a digital signal along a first clock-signal path to transmit the first clock signal along the control-signal channel.

35. An apparatus according to claim 34 that transmits

a vertical-synchronization signal along a vertical-synchronization-signal path, and

a horizontal-synchronication signal along a horizontal-synchronication-signal path;

and

wherein

the data-signal channel comprises two or more data-signal paths,

the control-signal channel comprises the first clock-signal path, the vertical-synchronization-signal path, and the horizontal-synchronication-signal path, and

the data-signal channel and the control-signal channel convey signals that are compatible with a liquid crystal display panel.

36. An apparatus according to claim 31 wherein a respective first signal component represents a respective pixel of the first image and a respective second signal component represents a respective pixel of the second image.

37. An apparatus according to claim 31 that comprises:

means for generating a sequence of third signal components representing components of a third image that is independent of the first and second images, wherein a respective third signal component represents a respective component of the third image that is narrower than the third image; and

means for transmitting along the data-signal channel the third signal components interleaved with the first and second signal components.

38. An apparatus according to claim 37 that comprises means for transmitting along the control-signal channel a second clock signal and a third clock signal, wherein a respective second signal component is aligned with a respective cycle of the second clock signal and a respective third signal component is aligned with a respective cycle of the third clock signal.

39. A plurality of display devices each comprising:

a plurality of image-data signal input connections;

a plurality of display-control signal input connections;

a clock signal input connection;

control circuitry having inputs in communication with the image-data signal input connections, the display-control signal input connections and the clock signal input connection, wherein the control circuitry receives from the image-data signal input connections a sequence of signals representing interleaved components of a plurality of independent images and extracts therefrom those components that are aligned with a clock signal received from the clock signal input connection, and wherein each component represents a portion of a respective image that is narrower than the respective image; and

a display screen in communication with outputs of the control circuitry;

wherein respective image-data signal input connections for the plurality display devices are coupled together and respective display-control signal input connections for the plurality display devices are coupled together, and respective clock signal input connections for the plurality of display devices are coupled to sources of respective clock signals.

40. A plurality of display devices according to claim 39 each having one or more liquid crystal display panels and comprising:

two or more image-data signal input connections; and

the plurality of display-control signal input connections that comprise a vertical-synchronization-signal input connection, and a horizontal-synchronicaton-signal input connection.

41. A plurality of display devices according to claim 39 wherein for each respective display device the control circuitry is adapted to receive from the image-data signal input connections a sequence signals representing interleaved components of a plurality of independent images and to extract therefrom those components that are aligned with a clock signal received from the clock signal input connection.

42. A plurality of display devices according to claim 41 wherein a respective component represents a respective pixel of an image.

43. An electrical socket comprising a plurality of electrical connections used to convey signals representing two or more independent images for presentation by two or more display devices, the electrical connections comprising:

a first clock-signal connection that conveys a first clock signal; and

a plurality of data-signal connections that convey a sequence of first signal components interleaved with a sequence of second signal components, wherein a respective first signal component represents a respective component of a first image that is narrower than the first image, a respective second signal component represents a respective component of a second image that is narrower than the second image, wherein the second image is independent of the first image, and a respective first signal component is aligned with a respective cycle of the first clock signal.

44. An electrical socket according to claim 43 that comprises a second clock-signal connection that conveys a second clock signal, wherein a respective second signal component is aligned with a respective cycle of the second clock signal.

45. An electrical socket according to claim 44 that comprises:

two or more data-signal connections;

a vertical-synchronization-signal connection; and

a horizontal-synchronication-signal connection.

46. An electrical socket according to claim 43 that comprises:

two or more data-signal connections;

a vertical-synchronization-signal connection; and

a horizontal-synchronication-signal connection.

47. An electrical socket according to claim 43 wherein a respective first signal component represents a respective pixel of the first image and a respective second signal component represents a respective pixel of the second image.