Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems

• US 6,628,537 B1
• Filed: 07/16/2002
• Issued: 09/30/2003
• Est. Priority Date: 04/11/1991
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Wallace, Robert F., Norman, Robert D.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/197,027
• Time in Patent Office: 441 Days
• Field of Search: 365/52, 365/63, 365/185.33, 711/103, 711/115, 710/301
• US Class Current: 365/52
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06K 19/07732 the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks housings for electrical equipment in general, see H05K5/02
• CPC Class Codes: G06K 19/07741 comprising a first part operating as a regular record carrier and a second attachable part that changes the functional appearance of said record carrier, e.g. a contact-based smart card with an adapter part which, when attached to the contact card makes the contact card function as a non-contact card
• CPC Class Codes: G06K 19/07743 External electrical contacts
• CPC Class Codes: G06K 7/0047 for reading/sensing record carriers having edge contacts
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2201/10462 Flat component oriented parallel to the PCB surface
• CPC Class Codes: H05K 2201/10484 Obliquely mounted
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/3421 : Leaded components
• CPC Class Codes: H05K 7/1431 : Retention mechanisms for CPU modules

Abstract

A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Claims

1. A system comprising:

a host system, comprising;

a computer system including a microprocessor; and

a host system connector to receive a memory card and connectable to (1) receiving address, user data and command signals from said host system according to a given protocol and (2) providing user data and status signals to said host system according to said given protocol;

a plurality of said memory cards which individually include a card connector that mechanically mates with the host system connector to provide a removable electrical connection therebetween, said card connector being connected to an integrated circuit array of floating gate memory cells organized in groups of cells that are individually addressable for simultaneous erasure of the cells of a group, said memory cards additionally being individually formed of a package having a width less than 5.5 centimeters and a length less than 9.0 centimeters;

a memory controller including at least one controller microprocessor that executes commands from the host system and a buffer memory that temporarily stores user data being written to or read from a memory card inserted in the host system connector, said memory controller additionally being responsive to an address of at least one mass memory storage block from the host system for accessing through said host system and card connectors a corresponding at least one of the memory cell groups within one of the plurality of memory cards having its card connector mated with said host system connector; and

a communication circuit including a serial portion extending through the host system and memory card connectors to transfer user data between the host system and said at least one accessed memory cell group.

2. The system of claim 1, wherein the host system connector is connected to the computer system through a cable.

3. The system of claim 1, wherein the host system connector is adapted to fit directly into the computer system.

4. The system of any one of claims claim 1-3, wherein the memory controller is individually included as part of each of said memory cards.

5. The system of any one of claims claim 1-3, wherein the memory controller is included as part of the host system.

6. The system according to claim 1, wherein said memory controller further includes:

a plurality of temporary storage registers, including at least one set for storing a storage block address received from the host system, a command register and a status

means for allowing the host system to write a storage block address to said one register set, to write a command to the command register, to read a status from the status register, to write user data into the buffer memory and to read user data from the buffer memory,

means including the controller microprocessor for reading from said one register set the address stored from the host system and translating said host system address into an address of one or more memory cell groups corresponding to the host system address, and

means including the controller microprocessor for reading the command register and (1) in response to a read command, transferring user data within the addressed at least one memory cell group into the buffer memory and then write a completion status in the status register, or (2) in response to a write command, transferring user data from the buffer memory into the addressed at least one memory cell group and write a completion status into the status register.

7. The system according to claim 1 wherein said memory system includes a second host connector to receive and connect the card connector of another of the plurality of said memory cards, thereby to establish operation of the controller simultaneously with two of said plurality of memory cards.

8. The system according to claim 1 wherein individual ones of the groups of memory cells that are simultaneously erasable include enough cells to store 512 bytes of user data plus overhead data related to a sector and the user data stored therein.

9. The system according to claim 1, wherein the memory cards individually include:

a plurality of sub-boards each carrying a plurality of flash EEPROM integrated circuit chips and including electrical conductors attached thereto which interconnect said chips to a plurality of electrical contacts along one edge of said sub-board, said contacts having a predetermined pattern therealong,

a main circuit board including electrical conductors attached thereto and extending between (a) a plurality of rows of electrical contacts on at least one side thereof that are each arranged in said pattern and (b) a plurality of electrical contacts at an edge thereof positioned to form part of a connector,

said sub-boards being attached to said main board with their edge contacts being electrically connected to respective ones of said plurality of rows of contacts on the main board, and

a cover enclosing said main printed circuit board and the attached sub-boards.

10. The system of claim 1, wherein the memory cells of the integrated circuit array are individually programmable into exactly two states in order to store exactly one bit of data per cell.

11. The system of claim 1, wherein the memory cells of the integrated circuit array are individually programmable into more than two states in order to store more than one bit of data per cell.

12. A host system adapted for use with a plurality of memory cards which individually include a card connector that mechanically mates with a host system connector to provide a removable electrical connection therebetween, said card connector being connected to an integrated circuit array of floating gate memory cells organized in groups of cells that are individually addressable for simultaneous erasure of the cells of a group, said memory cards additionally being individually formed of a package having a width less than 5.5 centimeters and a length less than 9.0 centimeters, the host system comprising:

a computer system including a microprocessor; and

a memory controller having a connector to receive said memory cards and connectable to (1) receiving address, user data and command signals from said memory cards according to a given protocol and (2) providing user data and status signals to said memory cards according to said given protocol, said controller including at least one controller microprocessor that executes commands from the computer system and a buffer memory that temporarily stores user data being written to or read from a memory card inserted in the controller connector,

said memory controller additionally being responsive to an address of at least one mass memory storage block from the host system for accessing through said controller and card connectors a corresponding at least one of the memory cell groups within one of the plurality of memory cards having its card connector mated with said controller connector, and

a communication circuit including a serial portion extending through the host system and controller connectors to transfer user data between the host system and said at least one accessed memory cell group.

13. The system of claim 12, wherein the memory controller is connected to the computer system through a cable.

14. The system of claim 12, wherein the memory controller is adapted to fit directly into the computer system.

15. The system according to claim 12, wherein said memory controller further includes:

a plurality of temporary storage registers, including at least one set for storing a storage block address received from the host system, a command register and a status register,

means for allowing the host system to write a storage block address to said one register set, to write a command to the command register, to read a status from the status register, to write user data into the buffer memory and to read user data from the buffer memory,

means including the controller microprocessor for reading from said one register set the address stored from the host system and translating said host system address into an address of one or more memory cell groups corresponding to the host system address, and

means including the controller microprocessor for reading the command register and (1) in response to a read command, transferring user data within the addressed at least one memory cell group into the buffer memory and then write a completion status in the status register, or (2) in response to a write command, transferring user data from the buffer memory into the addressed at least one memory cell group and write a completion status into the status register.

16. The system according to claim 12 wherein said memory system includes a second controller connector to receive and connect the card connector of another of the plurality of said memory cards, thereby to establish operation of the controller simultaneously with two of said plurality of memory cards.