Self-configuring input buffer on flash memories

• US 6,628,552 B1
• Filed: 04/11/1997
• Issued: 09/30/2003
• Est. Priority Date: 04/11/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Pon, Harry Q., Larsen, Robert E.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US08/834,029
• Time in Patent Office: 2,363 Days
• Field of Search: 365/189.05, 365/230.06, 365/185.05, 365/185.33
• US Class Current: 365/189.05
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A low-power input buffer for a nonvolatile writeable memory is described. The low-power input buffer accepts input signals having one of a number of pairs of logic levels. The low-power input buffer provides output signals having a pair of logic levels that may differ from the logic levels of the input signal. The low-power input buffer comprises an inverter that receives an input signal, a circuit with a relatively low voltage drop, and a feedback pull-up device. The circuit with the relatively low voltage drop causes the low-power input buffer to accept input signals having one pair of logic levels while providing signals that may have a different pair of logic levels. The feedback pull-up device prevents the low-power input buffer from drawing leakage current. The low-power input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply output as the nonvolatile writeable memory. The low-power input buffer uses input signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

Claims

1. An input buffer for a memory comprising:

an inverter configured to receive as inputs first and second separately defined logic high levels and a first separately defined logic low level; and

a driver configured to translate the output of the inverter to a third separately defined logic high level when the input to the inverter is either the first or second separately defined logic high level and to translate the output of the inverter to a second separately defined logic low level when the input to the inverter is the first separately defined logic low level;

the input buffer being self-configuring to accept as inputs the first and second separately defined logic high levels.

2. The input buffer of claim 1, wherein a circuit with a relatively low voltage drop is coupled to the inverter and to a power supply, the circuit having a threshold voltage, the circuit to prevent leakage current.

3. The input buffer of claim 1, wherein a feedback pull-up device is coupled to the driver and to a power supply, the feedback pull-up device to prevent leakage current.

4. The input buffer of claim 2, wherein the circuit is at least one high transconductance n-channel transistor doped to provide a threshold voltage that is lower than a standard n-channel transistor.

5. The input buffer of claim 4, wherein the threshold voltage is substantially equal to 0.3 volt.

6. The input buffer of claim 1, wherein the first separately defined logic high level is compatible with a first electrical system, the second separately defined logic high level is compatible with a second electrical system, and the first separately defined logic low level is compatible with the first and second electrical systems.

7. The input buffer of claim 6, wherein the first and second electrical systems are complementary metal-oxide semiconductor (CMOS) circuits.

8. The input buffer of claim 1, wherein the first separately defined logic high level equals 1.8 volts, the second separately defined logic high level equals 3.0 volts, the third separately defined logic high level equals 3.0 volts, the first separately defined logic low level equals 0 volt, and the second separately defined logic low level equals 0 volt.

9. The input buffer of claim 1, wherein the driver comprises an inverter having a p-channel transistor and a n-channel transistor, wherein a drain of the p-channel transistor is coupled to a drain of the n-channel transistor, wherein a source of the p-channel transistor is coupled to a power supply and a source of the n-channel transistor is coupled to ground.

10. The input buffer of claim 1, wherein the feedback pull-up device comprises a p-channel transistor, wherein a gate of the p-channel transistor is coupled to an output of the driver, wherein a source of the p-channel transistor is coupled to a power supply, and a drain of the p-channel transistor is coupled as an input to the driver.

11. The input buffer of claim 1, wherein the memory and the input buffer are coupled to a same power supply, the power supply providing a voltage substantially in the range from 2.7 volts to 2.85 volts.

12. The memory of claim 1, wherein the memory is a nonvolatile memory.

13. The memory of claim 12, wherein the memory is a flash memory.

14. A memory comprising:

(1) a memory array;

(2) an input buffer comprising;

an inverter configured to receive as inputs first and second separately defined logic high levels and a first separately defined logic low level; and

a driver configured to translate the output of the inverter to a third separately defined logic high level when the input to the inverter is either the first or second separately defined logic high level and to translate the output of the inverter to a second separately defined logic low level when the input to the inverter is the first separately defined logic low level;

the input buffer being self-configuring to accept as inputs the first and second separately defined logic high levels; and

(3) the memory array coupled to the input buffer.

15. The memory of claim 14, wherein a circuit with a relatively low voltage drop is coupled to the inverter and to a power supply, the circuit having a threshold voltage, the circuit to prevent leakage current.

16. The memory of claim 14, wherein a feedback pull-up device is coupled to the driver and to a power supply, the feedback pull-up device to prevent leakage current.

17. The memory of claim 15, wherein the circuit is at least one high transconductance n-channel transistor doped to provide a threshold voltage that is lower than a standard n-channel transistor.

18. The memory claim 17, wherein the threshold voltage substantially equal to 0.3 volt.

19. The memory of claim 14, wherein the first separately defined logic high level is compatible with a first electrical system, the second separately defined logic high level is compatible with a second electrical system, and the first separately defined logic low level is compatible with the first and second electrical systems.

20. The memory of claim 19, wherein the first and second electrical systems are complementary metal-oxide semiconductor (CMOS) circuits.

21. The memory of claim 14, wherein the first separately defined logic high level equals 1.8 volts, the second separately defined logic high level equals 3.0 volts, the third separately defined logic high level equals 3.0 volts, the first separately defined logic low level equals 0 volt, and the second separately defined logic low level equals 0 volt.

22. The memory of claim 14, wherein the driver comprises an inverter having a p-channel transistor and a n-channel transistor, wherein a drain of the p-channel transistor is coupled to a drain of the n-channel transistor, wherein a source of the p-channel transistor is coupled to a power supply and a source of the n-channel transistor is coupled to ground.

23. The memory of claim 14, wherein the feedback pull-up device comprises a p-channel transistor, wherein a gate of the p-channel transistor is coupled to an output of the driver, wherein a source of the p-channel transistor is coupled to a power supply, and a drain of the p-channel transistor is coupled as an input to the driver.

24. The memory of claim 14, wherein the memory and the input buffer are coupled to a same power supply, the power supply providing a voltage substantially in the range from 2.7 volts to 2.85 volts.

25. The memory of claim 14, wherein the memory is a nonvolatile memory.

26. The memory of claim 25, wherein the memory is a flash memory.

27. A processing system comprising:

(1) a processor;

(2) a memory comprising;

(a) a memory array;

(b) an input buffer comprising;

an inverter configured to receive as inputs first and second separately defined logic high levels and a first separately defined logic low level; and

a driver configured to translate the output of the inverter to a third separately defined logic high level when the input to the inverter is either the first or second separately defined logic high level and to translate the output of the inverter to a second separately defined logic low level when the input to the inverter is the first separately defined logic low level;

the input buffer being self-configuring to accept as inputs the first and second separately defined logic high levels;

(c) the memory array coupled to the input buffer; and

(3) the processor coupled to the memory.

28. The processing system of claim 27, wherein the first separately defined logic high level equals 1.8 volts, the second separately defined logic high level equals 3.0 volts, the third separately defined logic high level equals 3.0 volts, the first separately defined logic low level equals 0 volt, and the second separately defined logic low level equals 0 volt.

29. The processing system of claim 27, wherein the memory and the input buffer are coupled to a same power supply, the power supply providing a voltage substantially in the range from 2.7 volts to 2.85 volts.

30. The processing system of claim 27, wherein the memory is a nonvolatile memory.

31. The processing system of claim 30, wherein the nonvolatile memory is a flash memory.