Small anti-fuse circuit to facilitate parallel fuse blowing

• US 6,628,561 B2
• Filed: 08/30/2001
• Issued: 09/30/2003
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Van De Graaff, Scott
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/941,602
• Publication Number:
  US 20030043676A1
• Time in Patent Office: 761 Days
• Field of Search: 365/225.7, 365/96, 365/189.05, 327/525, 327/526, 327/54
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

An apparatus and associated method are provided to improve the programming of anti-fuse devices in an integrated circuit. A programming circuit capable of programming a plurality of anti-fuse devices in parallel permits a state-changing voltage to be applied to multiple anti-fuses substantially simultaneously using a common control signal.

Claims

1. A programming circuit for a plurality of programmable elements, said programming circuit comprising:

a plurality of programmable elements;

a plurality of element programming circuits each associated with a programmable element and each including

a latch circuit for receiving and holding a desired programming state of an associated programmable element, said plurality of element programming circuits setting the state of said associated programmable elements in accordance with a desired programming state held in an associated latch in response to a common control signal; and

a latch programming circuit for temporarily applying a programming signal to an input of a respective latch circuit, said latch circuit latching a state of said programming signal, said latch programming circuit comprising,

a latch isolation transistor coupled between said programmable element and said latch circuit, and

a latch-programming transistor having a gate controlled by a first latch-programming signal, a first source/drain coupled to a second latch-programming signal, and a second source/drain coupled to said input of said latch circuit through said latch isolation transistor.

2. A circuit as in claim 1, wherein each said latch circuit comprises:

an inverter circuit having an input coupled to an input of said latch circuit and an output coupled to an output of said latch circuit;

a pair of n-channel transistors connected in series between an input of said latch circuit and a first reference voltage;

a pair of p-channel transistors connected in parallel between said input of said latch circuit and a second reference voltage;

a read-and-latch signal line coupled to control gates of a first of said pair of p-channel transistors and a first of said pair of n-channel transistors;

wherein said output of said inverter circuit is coupled to control gates of a second of said pair of p-channel transistors and a second of said pair of n-channel transistors.

3. A circuit as in claim 2, wherein said read-and-latch signal line is configured to apply a read-and-latch signal to permit reading and latching of said desired programming signal.

4. A circuit as in claim 2, wherein a third p-channel transistor is coupled between said pair of parallel-connected p-channel transistors and said second reference voltage, said third p-channel transistor having a gate coupled to said first reference voltage.

5. A circuit as in claim 1, wherein said common control signal includes a voltage of between approximately 8 and 9 volts.

6. A circuit as in claim 1, wherein said common control signal includes a voltage sufficient to change a state of said associated programmable elements.

7. A programming circuit for a programmable element, comprising:

at least one latch circuit;

at least one latch-programming circuit for temporarily applying a programming signal to an input of a respective latch circuit, said latch circuit latching a state of said programming signal;

a signal line applying a voltage sufficient to change the state of said programmable element;

at least one latch isolation transistor coupled between said programmable element and said latch circuit;

at least one state control transistor coupled between said programmable element and a first reference voltage and having a gate controlled by an output of said latch circuit;

wherein said at least one latch-programming circuit further comprises, at least one latch-programming transistor having a gate controlled by a first latch-programming signal, a first source/drain coupled to a second latch-programming signal, and a second source/drain coupled to said input of said latch circuit through one of said at least one latch isolation transistor, and

wherein during a programming phase, said latch circuit is configured to latch said programming signal, and during a common control phase, said latch isolation transistor is configured to decouple said programmable element from said latch circuit and said signal line is configured to apply said state-changing voltage to said programmable element if said output of said latch circuit turns on said state control transistor.

8. A circuit as in claim 7, wherein said at least one latch circuit comprises:

an inverter circuit having an input coupled to said input of said latch circuit and an output coupled to said output of said latch circuit;

a pair of n-channel transistors connected in series between an input of said latch circuit and said first reference voltage;

a pair of p-channel transistors connected in parallel between said input of said latch circuit and a second reference voltage;

a read-and-latch signal line coupled to control gates of a first of said pair of p-channel transistors and a first of said pair of n-channel transistors;

wherein said output of said inverter circuit is coupled to control gates of a second of said pair of p-channel transistors and a second of said pair of n-channel transistors.

9. A circuit as in claim 8, wherein said read-and-latch signal line is configured to apply a read-and-latch signal during said programming phase to permit reading and latching of said programming signal.

10. A circuit as in claim 8, wherein a third p-channel transistor is coupled between said pair of parallel-connected p-channel transistors and said second reference voltage, said third p-channel transistor having a gate coupled to said first reference voltage.

11. A circuit as in claim 7, further comprising at least one programming enable transistor configured to couple said state control transistor to said programmable element during said common control phase.

12. A circuit as in claim 7, further comprising at least one programmable element isolation transistor configured to decouple said programmable element from said latch circuit and said latch-programming circuit during said programming phase.

13. A circuit as in claim 7, wherein said state-changing voltage includes a voltage sufficient to blow an anti-fuse.

14. A circuit as in claim 7, wherein during said common control phase, said state-changing voltage of between approximately 8 and 9 volts is applied to said signal line.

15. A memory circuit, comprising:

a plurality of memory elements; and

at least one programming circuit associated with a plurality of programmable elements and configured to activate one or more of said plurality of memory elements, said programming circuit comprising;

a plurality of programmable elements;

a plurality of element programming circuits each associated with a programmable element and each including

a latch circuit for receiving and holding a desired programming state of an associated programmable element, said plurality of element programming circuits setting the state of said associated programmable elements in accordance with a desired programming state held in an associated latch in response to a common control signal; and

a latch programming circuit for temporarily applying a programming signal to an input of a respective latch circuit, said latch circuit latching a state of said programming signal, said latch programming circuit comprising,

a latch isolation transistor coupled between said programmable element and said latch circuit, and

a latch-programming transistor having a gate controlled by a first latch-programming signal, a first source/drain coupled to a second latch-programming signal, and a second source/drain coupled to said input of said latch circuit through said latch isolation transistor.

16. A memory circuit as in claim 15, wherein said common control signal includes a voltage of between approximately 8 and 9 volts.

17. A memory circuit as in claim 16, wherein each said latch circuit comprises:

an inverter circuit having an input coupled to an input of said latch circuit and an output coupled to an output of said latch circuit;

a pair of n-channel transistors connected in series between an input of said latch circuit and a first reference voltage;

a pair of p-channel transistors connected in parallel between said input of said latch circuit and a second reference voltage;

a read-and-latch signal line coupled to control gates of a first of said pair of p-channel transistors and a first of said pair of n-channel transistors;

wherein said output of said inverter circuit is coupled to control gates of a second of said pair of p-channel transistors and a second of said pair of n-channel transistors.

18. A memory circuit as in claim 17, wherein said read-and-latch signal line is configured to apply a read-and-latch signal to permit reading and latching of said desired programming signal.

19. A memory circuit as in claim 17, wherein a third p-channel transistor is coupled between said pair of parallel-connected p-channel transistors and said second reference voltage, said third p-channel transistor having a gate coupled to said first reference voltage.

20. A memory circuit, comprising:

a plurality of memory elements; and

at least one programming circuit associated with a plurality of programmable elements and configured to activate one or more of said plurality of memory elements, said programming circuit comprising;

at least one latch circuit;

at least one latch-programming circuit for temporarily applying a programming signal to an input of a respective latch circuit, said latch circuit latching a state of said programming signal;

a signal line applying a voltage sufficient to change the state of said programmable element;

at least one latch isolation transistor coupled between said programmable element and said latch circuit;

at least one state control transistor coupled between said programmable element and a first reference voltage and having a gate controlled by an output of said latch circuit;

wherein said latch-programming circuit comprises at least one latch-programming transistor having a gate controlled by a first latch-programming signal, a first source/drain coupled to a second latch-programming signal, and a second source/drain coupled to said input of said latch circuit through one of said at least one latch isolation transistor;

wherein during a programming phase, said latch circuit is configured to latch said programming signal, and during a common control phase, said latch isolation transistor is configured to decouple said programmable element from said latch circuit and said signal line is configured to apply said state-changing voltage to said programmable element if said output of said latch circuit turns on said state control transistor.

21. A memory circuit as in claim 20, wherein during said common control phase, said state-changing voltage of between approximately 8 and 9 volts is applied to said signal line.

22. A memory circuit as in claim 20, wherein said at least one latch circuit comprises:

an inverter circuit having an input coupled to said input of said latch circuit and an output coupled to said output of said latch circuit;

a pair of n-channel transistors connected in series between an input of said latch circuit and said first reference voltage;

a pair of p-channel transistors connected in parallel between said input of said latch circuit and a second reference voltage;

a read-and-latch signal line coupled to control gates of a first of said pair of p-channel transistors and a first of said pair of n-channel transistors;

wherein said output of said inverter circuit is coupled to control gates of a second of said pair of p-channel transistors and a second of said pair of n-channel transistors.

23. A memory circuit as in claim 22, wherein said read-and-latch signal line is configured to apply a read-and-latch signal during said programming phase to permit reading and latching of said programming signal.

24. A memory circuit as in claim 22, wherein a third p-channel transistor is coupled between said pair of parallel-connected p-channel transistors and said second reference voltage, said third p-channel transistor having a gate coupled to said first reference voltage.

25. A memory circuit as in claim 20, further comprising at least one programming enable transistor configured to couple said state control transistor to said programmable element during said common control phase.

26. A memory circuit as in claim 20, further comprising at least one programmable element isolation transistor configured to decouple said programmable element from said latch circuit and said latch-programming circuit during said programming phase.