Programmable packet switching device

• US 6,628,653 B1
• Filed: 06/04/1998
• Issued: 09/30/2003
• Est. Priority Date: 06/04/1998
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Salim, Jamal Hadi
• Primary Examiner(s): Nguyen, Chau
• Assistant Examiner(s): TRINH, DUNG N
• Application Number:
  US09/090,285
• Time in Patent Office: 1,944 Days
• Field of Search: 370/389, 370/392, 370/401, 370/402, 370/403, 370/404, 370/405
• US Class Current: 370/389
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 61/00 Network arrangements, protocols or services for addressing or naming
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A packet processing apparatus comprises a programmable hardware discriminator for receiving incoming packets, and selecting bits from any part of the incoming packets, a decision table for storing information relating to how the packets are to be processed, programmable hardware searching logic for accessing the information in the table according to the selected bits, and a packet handler for processing the packets according to the result of the access. Since many networking processing tasks can be broken down into bit selection and table searching, this generic type of arrangement will suit a wide variety of applications. It facilitates developing logic directly in hardware which can reduce the effort needed to convert a working prototype into a product ready for use in the field, e.g. for handling new protocol components.

Claims

1. A method of reconfiguring a packet processor, the packet processor comprising:

a programmable hardware discriminator for receiving incoming packets, and selecting bits from any part of the incoming packets;

a decision table containing information relating to how the packets are to be processed; and

programmable hardware searching logic coupled to the decision table and to the discriminator for accessing the information in the table according to the selected bits, the method comprising the steps of;

determining a column structure for the decision table;

determining which bits to select from each packet;

determining a correspondence between the selected bits and the columns of the table;

determining which bits are to be used in the search;

deriving a new configuration for the discriminator on the basis of the determination of which bits to select;

deriving a new configuration for the searching logic on the basis of the column structure, which bits are to be used in the search, and the correspondence; and

loading the new configurations into the searching logic, and the discriminator respectively.